Timer Description
6-4
Table 6–2 provides division values for each PTV field.
Table 6–2. PTV Value and Corresponding Division Value
PTV
Divisor
0
2
1
4
2
8
3
16
4
32
5
64
6
128
7
256
The timer interrupt period is determined in the following manner, where t
clk
is
the clock period of the input clock, LOAD_TIM (see Table 6–1) is the register
that holds the value loaded when the timer passes through 0 or when it starts,
and PTV is the prescaler field located in the control timer register
(CNTL_TIMER):
t
int
= t
clk
X (LO 1) x 2
(PTV+1)
Table 6–3 shows the timer characteristics for the three timers for different input
frequencies.
Table 6–3. Timer Characteristics
Input Clock
t
clk
, Clock
Period
LOAD_TIM
t
int
, Timer
Interrupt
Period, for
PTV = 0
t
int
, Timer Interrupt Period,
for PTV = 7
100 MHz
10 ns
0000 0001
40 ns
5.12
µ
s
100 MHz
10 ns
FFFF FFFF (max
interrupt period)
85.9 s
10995 s (3 hr 3’ 25”)
12 MHz
83.3 ns
0000 0001
333.4 ns
42.64
µ
s
12 MHz
83.3 ns
FFFF FFFF (max
interrupt period)
715.5 s
91589 s (25 hr, 26’29”)
