Texas Instruments OMAP5910, Technical Reference Manual

Page: 216 / 1209

Traffic Controller Memory Interface Registers
4-42
4.4 Traffic Controller Memory Interface Registers
OMAP5910 traffic controller base address is 0xFFFE:CC00.
Table 4–8 lists the traffic controller registers. Table 4–9 through Table 4–27
describe the register bits.
The EMIF slow interface configuration register provides access to EMIFS
boot, operation, and power-down options (see Table 4–12).
Table 4–8. Traffic Controller Registers
Name Description R/W Size Address Reset Value
IMIF_PRIO IMIF priority register R/W 32 bits 0xFFFE:CC00 0x0000 0000
EMIFS_PRIO EMIF slow priority register R/W 32 bits 0xFFFE:CC04 0x0000 0000
EMIFF_PRIO EMIF fast priority register R/W 32 bits 0xFFFE:CC08 0x0000 0000
EMIFS_CONFIG_REG EMIF slow interface
configuration register R/W 32 bits 0xFFFE:CC0C 0x0000 00yy
(See
Table 4–12
for details on
the y values.)
EMIFS_CS0_CONFIG EMIF slow interface
chip-select configuration
register nCS0 R/W 32 bits 0xFFFE:CC10 0x0000 FFFB
EMIFS_CS1_CONFIG EMIF slow interface
chip-select configuration
register nCS1 R/W 32 bits 0xFFFE:CC14 0x0010 FFFB
EMIFS_CS2_CONFIG EMIF slow interface
chip-select configuration
register nCS2 R/W 32 bits 0xFFFE:CC18 0x0010 FFFB
EMIFS_CS3_CONFIG EMIF slow interface
chip-select configuration
register nCS3 R/W 32 bits 0xFFFE:CC1C 0x0000 FFFB
EMIFF_SDRAM_CONFIG EMIF fast interface SDRAM
configuration register 1 R/W 32 bits 0xFFFE:CC20 0x0061 8800
EMIFF_MRS EMIF fast interface SDRAM
MRS register R/W 32 bits 0xFFFE:CC24 0x0000 0037
TIMEOUT1 Timeout1 R/W 32 bits 0xFFFE:CC28 0x0000 0000
TIMEOUT2 Timeout2 R/W 32 bits 0xFFFE:CC2C 0x0000 0000
TIMEOUT3 Timeout3 R/W 32 bits 0xFFFE:CC30 0x0000 0000