Clock Generation and Reset Control Registers
15-66
The DSP idle mode entry 1 register (DSP_IDLECT1) enables and defines the
idle mode entry/exit to each clock domain.
Table 15–20. DSP Idle Mode Entry 1 Register (DSP_IDLECT1) – Offset Address: 0x04
Bit
Name
Value
Description
Type
Reset
Value
15–9
RESERVED
Reading these bits gives undefined values. Writing
to them has no effect.
8
IDLTIM_DSP
Selects idle entry mode for internal DSP timer clock
(DSPTIM_CK).
R/W
0
0
The DSPTIM_CK clock remains active when DSP
enters idle mode.
1
The DSPTIM_CK clock is stopped in conjunction
with DSP clock when idle mode is set (DSP_IDLE
signal asserted high).
7
RESERVED
R/W
0
6
RESERVED
Reserved. To prevent errant behavior, this bit should
always be written as 1.
R/W
1
5–2
RESERVED
Reserved. To prevent errant behavior, these bits
should always be written as o.
R/W
0
1
IDLXORP_DSP
Selects idle entry mode for reference peripheral
clock (DSPXOR_CK).
R/W
0
0
The DSPXOR_CK clock remains active when DSP
enters idle mode.
1
The DSPXOR_CK clock is stopped in conjunction
with DSP clock when idle mode is entered.
0
IDLWDT_DSP
Selects idle entry mode for timer/watchdog
connected to DSP TIPB.
R/W
0
0
The clock supplied to timer/watchdog remains
active when the DSP enters idle mode.
1
The timer/watchdog clock is stopped in conjunction
with the DSP clock when idle mode is entered.
Note:
When the timer/watchdog is configured as watchdog timer, the clock is never shutdown, regardless of the value of the
IDLWDT_DSP bit.
