Clock Generation and Reset Control Registers
15-61
Clock Generation and System Reset Management
The MPU reset control 2 register (ARM_RSTCT2) sets the PER_EN signal
that resets peripherals attached to the MPU.
Table 15–14. MPU Reset Control 2 Register (ARM_RSTCT2)
Bit
Name
Value
Description
Type
Reset
Value
15–1
RESERVED
Reading these bits gives undefined values. Writing
to them has no effect.
0
PER_EN
Controls MPUPER_nRST signal used to reset and/
or enable peripherals connected to MPU TIPB:
R/W
0
0
ARMPER_nRST signal active
1
ARMPER_nRST signal inactive
The MPU system status register (ARM_SYSST) contains the system informa-
tion such as processor state, chip configuration, and reset status flags.
Table 15–15. MPU System Status Register (ARM_SYSST)
Bit
Name
Value
Description
Type
Reset
Value
15–14 RESERVED
Reading these bits gives undefined values. Writing
to them has no effect.
13–11 CLOCK_SELECT
(2–0)
The CLOCK_SELECT bits indicate the current
clocking scheme selection: the application can
switch OMAP5910 clocking scheme by writing to
these bits. These bits are at logic 0 after reset
(select fully synchronous clocking scheme) (see
Table 15–16).
R/W
0
10–7
RESERVED
6
IDLE_DSP
Indicates DSP state:
R
0
0
DSP active
1
DSP in global idle state
5
POR
Indicates (in conjunction with EXT_RST bit) whether
or not a power-on reset (cold start) has occurred.
Writing it to logic 0 clears this bit. This bit cannot be
written to logic 1 from TIPB interface:
R/C
0
0
No power-on reset detected
1
A power-on reset occurred
