Clock Generation
15-10
15.2.2 Operating Modes
The OMAP5910 device supports the following operating modes:
-
Fully synchronous
MPU, DSP MMU, and TC run at the same clock period, and DSP MMU is
1x or 1/2x of DSP. For example, DPLL1 output can be 120 MHz; MPU,
DSP MMU, and TC can be 60 MHz; and DSP can be 120 MHz.
On power up, the OMAP5910 device is always in synchronous mode,
where MPU, DSP MMU, TC, and DSP are all at the same speed.
-
Synchronous scalable
MPU, DSP MMU, and TC are synchronous, but MPU and DSP MMU are
multiples (1x, 2x, 4x, or 8x) of TC. The DSP must be 1x or 2x of the DSP
MMU. For example, DPLL1 clock can be 120 MHz, MPU can run at 120
MHz, DSP MMU can run at 60 MHz, TC can run at 30 MHz, and DSP can
run at 60 MHz or 120 MHz. In this mode, the clock-feeding mechanism (to
each respective domain) is similar to that of the fully synchronous mode,
with the exception that the clocks are synchronous but are multiples of
each other. The input clock is from DPLL1, and the clock is multiplied/
divided by the CLKM (1, 2, 3) as in the following example (assuming the
output of DPLL1 is 120 MHz):
J
CLKM1 output: 120 MHz/2
J
CLKM2 output: 120 MHz/1
J
CLKM3 output: 120 MHz/4
Divider circuitry is implemented in each CLKM.
Note:
In synchronous scalable mode, the traffic controller clock must have the
same or a slower frequency as the MPU and the DSPMMU clock.
At reset, the fully synchronous mode is selected (default). After the
OMAP5910 device is up and running, the application software can write to the
control registers via the CLOCK_SELECT (2:0) bits in the MPU system status
register (ARM_SYSST) to switch to a desired mode of operation. However,
you should use the system software to save the context before switching
modes. For information about the switching procedure, see Appendix B,
Switching Clock Modes.
The DSP_MMU clock must obey all of the following rules:
1) TC clock frequency always must be equal to or less than DSP, DSPMMU,
and MPU clocks.
