Introduction
15-7
Clock Generation and System Reset Management
-
Wake up initiated by interrupts (MPU, DSP, and TCLB_EN pin) or DMA
requests (TC and peripheral bus) in the idle mode
-
Unmasked interrupt events enabled to wake up the device during idle
modes
15.1.1.4
Memory-Mapped Registers
The application program controls the clock generation, reset, and power-
saving modes via a set of memory-mapped registers (nine 16-bit registers for
MPU subsystem and seven 16-bit registers for the DSP subsystem). These
registers are accessible by the MPU or the DSP processors.
The MPU is the master of the OMAP5910 device at all times, and it controls
the activities in the MPU, DSP, and TC domains.
The DSP controls DSP peripheral activities.
15.1.1.5
Clock Domains
The OMAP5910 is partitioned into three clock domains, each with its own clock
manager:
-
MPU domain (CLKM1)
-
DSP domain (CLKM2)
-
TC domain (CLKM3)
Clock domains use a common DPLL to provide a synchronous clock. The
different clocking configurations are discussed in detail later in this chapter.
The external clock source (OSC1_IN) frequency must be 12 MHz to ensure
proper operation for the USB.
