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IVA2.2 Subsystem Register Manual
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Table 5-375. Register Call Summary for Register TPCC_QER_Rn
IVA2.2 Subsystem Register Manual
•
Table 5-376. TPCC_QEER_Rn
Address Offset
(0x200*n) n = 0 to 7
Physical address
0x01C0 2084 + (0x200*n) n = 0 to 7
Instance
IVA2.2 TPCC
Description
QDMA Event Enable Register:
Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA
channels can be enabled through writes to QEESR and can be disabled through writes to QEECR register.
QEER.En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and
latched in QER.En.
QEER.En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in
QER.En.
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
E7
E6
E5
E4
E3
E2
E1
E0
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Read returns 0.
R
0x000000
7
E7
Event #7
R
0
6
E6
Event #6
R
0
5
E5
Event #5
R
0
4
E4
Event #4
R
0
3
E3
Event #3
R
0
2
E2
Event #2
R
0
1
E1
Event #1
R
0
0
E0
Event #0
R
0
Table 5-377. Register Call Summary for Register TPCC_QEER_Rn
IVA2.2 Subsystem Register Manual
•
Table 5-378. TPCC_QEECR_Rn
Address Offset
(0x200*n) n = 0 to 7
Physical address
0x01C0 2088 + (0x200*n) n = 0 to 7
Instance
IVA2.2 TPCC
Description
QDMA Event Enable Clear Register:
CPU write of 1 to the QEECR.En bit causes the QEER.En bit to be cleared.
CPU write of 0 has no effect.
Type
W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
E7
E6
E5
E4
E3
E2
E1
E0
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Write 0s for future compatibility.
W
0x000000
7
E7
Event #7
W
0
6
E6
Event #6
W
0
5
E5
Event #5
W
0
4
E4
Event #4
W
0
946
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated