Public Version
IVA2.2 Subsystem Register Manual
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Table 5-319. Register Call Summary for Register TPCC_QEESR
IVA2.2 Subsystem Register Manual
•
Table 5-320. TPCC_QSER
Address Offset
0x1090
Physical address
0x01C0 1090
Instance
IVA2.2 TPCC
Description
QDMA Secondary Event Register:
The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on
the state of a QDMA Event.
En = 0: Event is not currently in the Event Queue.
En = 1: Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
E7
E6
E5
E4
E3
E2
E1
E0
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Write 0s for future compatibility.
W
0x000000
7
E7
Event #7
W
0
6
E6
Event #6
W
0
5
E5
Event #5
W
0
4
E4
Event #4
W
0
3
E3
Event #3
W
0
2
E2
Event #2
W
0
1
E1
Event #1
W
0
0
E0
Event #0
W
0
Table 5-321. Register Call Summary for Register TPCC_QSER
IVA2.2 Subsystem Register Manual
•
Table 5-322. TPCC_QSECR
Address Offset
0x1094
Physical address
0x01C0 1094
Instance
IVA2.2 TPCC
Description
QDMA Secondary Event Clear Register:
The secondary event clear register is used to clear the status of the QSER and QER register (note that this is
slightly different than the SER operation, which does not clear the ER.En register).
CPU write of 1 to the QSECR.En bit clears the QSER.En and QER.En register fields.
CPU write of 0 has no effect.
Type
W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
E7
E6
E5
E4
E3
E2
E1
E0
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Write 0s for future compatibility.
W
0x000000
7
E7
Event #7
W
0
6
E6
Event #6
W
0
5
E5
Event #5
W
0
4
E4
Event #4
W
0
920
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated