Public Version
IVA2.2 Subsystem Basic Programming Model
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5.4.10 IVA2.2 Power Management
5.4.10.1 Clock Management
5.4.10.1.1 Clock Configuration
The IVA2.2 subsystem receives one single-clock signal from the PRCM, the DPLL2_ALWON.FCLK.
From the DPLL2_ALWON.FCLK functional clock provided by the PRCM, three internal clocks (CD0_CLK,
CD1_CLK, and CD2_CLK) are generated by the IVA2.2 DPLL and SYSC modules:
•
The frequency of the CD0_CLK clock can be software-tuned with a PRCM register by setting the
PRCM.CM_CLKSEL1_PLL_IVA2 and PRCM.CM_CLKSEL2_PLL_IVA2 registers.
•
The CD1_CLK clock is always a divide-by-two of the CD0_CLK clock and its frequency cannot be
changed by software.
•
The CD2_CLK clock is always a divide-by-two of the CD0_CLK clock and its frequency cannot be
changed by software.
For a complete description of the PRCM registers discussed in this section, see
, Power, Reset,
and Clock Management.
5.4.10.1.2 Clock Gating
•
IVA2.2 subsystem
The IVA2.2 internal clocks can be hardware-disabled by the PRCM when the MSTANDBY/WAIT
handshake protocol occurs. To configure the PRCM so that IVA2.2 internal clocks are
hardware-supervised, set the PRCM.CM_AUTOIDLE_PLL_IVA2[2:0] AUTO_IVA2_DPLL field to 0x1.
When the IVA2.2 subsystem does not require its internal clocks, they can be disabled at the PRCM
level by setting the PRCM.CM_FCLKEN_IVA2[0] EN_IVA2 bit to 0.
For a complete description of these PRCM registers, see
, Power, Reset, and Clock
Management.
•
SYSC module
The IVA2.2 SYSC module implements automatic clock gating on internal hardware detection of the
absence of activity. The transition from clock-gated to clock-nongated state is operated with no cycle
latency penalty.
The automatic clock-gating feature is enabled by setting the IVA_SYSC.
AUTOIDLE bit to 1 (default value). This feature can be disabled by setting the
IVA_SYSC.
[0] AUTOIDLE bit to 0 and making the clock free-running.
•
WUGEN module
The IVA2.2 WUGEN module implements automatic clock gating on internal hardware detection of the
absence of activity. The transition from clock-gated to clock-nongated state operates with no cycle
latency penalty.
Automatic clock gating is enabled by setting the IVA_WUGEN.
[0] AUTOIDLE bit
to 1 (default mode). The clock can be made free-running by setting the
IVA_WUGEN.
[0] AUTOIDLE bit to 0.
•
TPCC from EDMA module
The EDMA (or TPCC) module implements automatic clock gating on internal hardware detection of the
absence of activity. The transition from clock-nongated to clock-gated state operates with no cycle
latency penalty.
5.4.10.2 Reset Management
In addition to hardware reset signals generated by the PRCM, the IVA2.2 subsystem can be reset by
software control.
The three DSP power domain software resets (DSP_RST1, DSP_RST2, and DSP_RST3) are partial
warm-reset sources. These software resets map to the PRCM.RM_RSTCTL_IVA2[0] RST1_IVA2 bit, the
RM_RSTCTRL_IVA2[1] RST2_IVA2 bit, and the PRCM.RM_RSTCTL_IVA2[2] RST3_IVA2 bit,
respectively, in the PRCM register RM_RSTCTRL_IVA2.
796
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated