Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 730 / 3738

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IVA2.2 Subsystem Functional Description
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5.3.4 Video Accelerator/Sequencer Local Interconnect
The video accelerator/sequencer local interconnect allows the DSP megamodule and the sequencer to
access the coprocessor, the sequence and video accelerator system control, the shared L2 memory
interface, and the IVA2.2 EDMA.
All sequencer reads and writes are performed through the video accelerator/sequencer local interconnect.
The DSP can access the interconnect with EFI instructions (EFSDW, EFSW, EFRW, and EFRDW). A
write is always composed of an EFSDW (32b). Depending on the destination value associated with the
instruction, the pair of DSP megamodule registers contains either the address (32b; only the lowest 20 bits
are significant) and the 32b data, or only the 64b data (auto-incrementing, constant addressing mode). A
read is composed of a pair of EFSW and EFRW or EFRDW, depending on the size of the read data. For
consistency, reads have the same addressing modes as writes.
NOTE: The DSP accesses the shared L2 memory and the IVA2.2 EDMA through the IVA
interconnect.
Table 5-6 shows the video accelerator/sequencer interconnect memory mapping. Addresses correspond
to the DSP megamodule address using the EFI instruction.
For more information about EFI instruction in IVA2.2, see Section 5.4.5 , IVA2.2 Extended Function
Interface.
Table 5-6. Video Accelerator/Sequencer Memory Mapping
Device Name Start Address End Address Size Description
(Hex) (Hex)
L2 memory 0x0 0000 0x0 7FFF 32KB L2 shared SRAM
Reserved 0x0 8000 0x1 FFFF 96KB Reserved
DMA registers 0x2 0000 0x3 FFFF 128KB Configuration registers
Reserved 0x4 0000 0x7 FFFF 256KB Reserved
iVLCD registers 0x8 0000 0x8 1FFF 8KB Configuration registers
Reserved 0x8 2000 0x8 3FFF 8KB Reserved
iVLCD IBUF0_A 0x8 4000 0x8 43FF 1KB iVLCD image buffer 0 part A
Reserved 0x8 4400 0x8 4FFF 3KB Reserved
iVLCD IBUF0_B 0x8 5000 0x8 53FF 1KB iVLCD image buffer 0 part B
Reserved 0x8 5400 0x8 5FFF 3KB Reserved
iVLCD IBUF1 0x8 6000 0x5 6BFF 3KB iVLCD image buffer 1
Reserved 0x8 6C00 0x8 7FFF 5KB Reserved
iVLCD QMEM 0x8 8000 0x8 83FF 1KB iVLCD quantizer memory
Reserved 0x8 8400 0x8 BFFF 15KB Reserved
iVLCD HMEM 0x8 C000 0x8 DBFF 7KB iVLCD Huffman memory
Reserved 0x8 DC00 0x8 FFFF 9KB Reserved
SEQ registers 0x9 0000 0x9 07FF 2KB Configuration registers
Reserved 0x9 0800 0x9 0FFF 2KB Reserved
Reserved 0x9 1000 0x9 3FFF 12KB Reserved
SEQ DMEM 0x9 4000 0x9 4FFF 4KB Sequencer data memory
Reserved 0x9 5000 0x9 7FFF 12KB Reserved
SEQIMEM 0x9 8000 0x9 9FFF 8KB Sequencer instruction memory
Reserved 0x9 A000 0x9 BFFF 8KB Reserved
Video SYSC registers 0x9 C000 0x9 CFFF 4KB Configuration registers
Reserved 0x9 D000 0x9 FFFF 12KB Reserved
iME registers 0xA 0000 0xA 0FFF 4KB Configuration registers
iLF registers 0xA 1000 0xA 1FFF 4KB Configuration registers
Reserved 0xA 2000 0xF 7FFF 344KB Reserved
730 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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