Cortex-A8 MPU subsystem
Local interconnect
ARM Cortex-A8 CPU
Neon
core
Trace/debug
L2 cache controller
256 KB cache
Interrupt
controller
MPU_INTRC_FIQ
MPU_INTRC_IRQ
Emulation/ICE-Crusher
to L3
DPLL/clock/reset
generator
PRCM
Bridge
mpu-006
Public Version
MPU Subsystem Overview
www.ti.com
4.1
MPU Subsystem Overview
4.1.1 Introduction
The MPU subsystem of the device handles transactions among the ARM
®
core, the L3 interconnect, and
the interrupt controller (INTC).
The MPU subsystem is hard-macro, thus integrating the ARM subchip with additional logic for protocol
conversion, emulation, interrupt handling, and debug enhancements.
shows the high-level
block diagram of the MPU subsystem.
Figure 4-1. MPU Subsystem Overview
4.1.2 Features
The MPU subsystem integrates the following:
•
ARM subchip
–
ARM Cortex™-A8 core revision r3p2. For more information, refer to the ARM Cortex-A8 TRM.
–
ARM Version 7 ISA™: Standard ARM instruction set + Thumb
®
-2, JazelleX™ Java™ accelerator,
and media extensions
–
ARM NEON™ core - single instruction, multiple data (SIMD) coprocessor (VFP light + media
streaming instructions)
–
Cache memories
676
MPU Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated