Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 3654 / 3738

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Memory Mapping
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Table A-1. L3 Control Register Mapping (continued)
Device Name Start Address End Address Size (KB) Description
(Hex) (Hex)
Reserved 0x6801 3400 0x6801 3FFF 3 Reserved
IVA2.2 PM 0x6801 4000 0x6801 43FF 1 IVA2.2 subsystem target port protection
Reserved 0x6801 4400 0x68FF FFFF 16,303 Reserved
A.2.2.2 L4 Memory Space Mapping
The device contains four L4 interconnects:
• L4-Core
• L4-Wakeup
• L4-Per
• L4-Emu
A.2.2.2.1 L4-Core Memory Space Mapping
The L4-Core interconnect is a 16-MB space composed of the L4-Core interconnect configuration registers
and the module registers.
Table A-2 describes the mapping of the registers for the L4-Core interconnect.
NOTE: All memory spaces described as modules provide direct access to module registers outside
the L4-Core interconnect. All other accesses are internal to the L4-Core interconnect.
Table A-2. L4-Core Memory Space Mapping
(1)
Device Name Start Address End Address Size Description
(Hex) (Hex)
L4-Core 0x4800 0000 0x48FF FFFF 16MB
Reserved 0x4800 0000 0x4800 1FFF 8KB Reserved
System control module (SCM) 0x4800 2000 0x4800 2FFF 4KB Module
0x4800 3000 0x4800 3FFF 4KB L4 interconnect
Clock manager 0x4800 4000 0x4800 5FFF 8KB Module region A
• DPLL
0x4800 6000 0x4800 67FF 2KB Module region B
• Clock manager
0x4800 6800 0x4800 6FFF 2KB Reserved
0x4800 7000 0x4800 7FFF 4KB L4 interconnect
Reserved 0x4800 8000 0x4802 3FFF 112KB Reserved
Reserved 0x4802 4000 0x4802 4FFF 4KB Reserved
0x4802 5000 0x4802 5FFF 4KB Reserved
Reserved 0x4802 6000 0x4803 FFFF 104KB Reserved
L4-Core configuration 0x4804 0000 0x4804 07FF 2KB Address/protection (AP)
0x4804 0800 0x4804 0FFF 2KB Initiator port (IP)
0x4804 1000 0x4804 1FFF 4KB Link agent (LA)
Reserved 0x4804 2000 0x4804 FBFF 55KB Reserved
Display subsystem 0x4804 FBFF 0x4804 FFFF 1KB DSI
• DSI
0x4805 0000 0x4805 03FF 1KB Display subsystem top
• Display subsystem top
0x4805 0400 0x4805 07FF 1KB Display controller
• Display controller (DISPC)
0x4805 0800 0x4805 0BFF 1KB RFBI
• RFBI
0x4805 0C00 0x4805 0FFF 1KB Video encoder
• Video encoder (VENC)
0x4805 1000 0x4805 1FFF 4KB L4 interconnect
(1)
The registers mapped in this range are shadow registers of the first 2-KB region A [0x4800 4000 – 0x4800 47FF]. Region A and region B
share the same port.
3654 OMAP36xx Multimedia Device in CYN Package SWPU177N – December 2009 – Revised November 2010
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