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General-Purpose Interface Integration
set to 1, this bit forces clock gating for all internal clock paths. Module internal activity is suspended.
The L4 interconnect is not affected by this bit.
Each 8-input group of GPIO has a clock-enable signal that can be enabled or disabled depending on the
edge/level detection register setting. If a group requires no detection, then the corresponding clock is
gated.
The interface clock gating is controlled with the GPIOi.
[0] AUTOIDLE bit, which is
used to save power when the module is not used because of the multiplexing configuration selected at the
chip level. This bit has precedence over all other internal configuration bits.
25.3.1.2 Hardware Requests
25.3.1.2.1 Interrupt Requests
All interrupt sources (the 32 input GPIO channels) are merged to issue two synchronous interrupt requests
in each GPIO module. Thus, the general-purpose interface has 12 interrupt lines (two interrupt lines per
GPIO module instance).
Synchronous interrupt request lines 1 and 2 are active depending on their respective interrupt-enable 1
and 2 registers (GPIOi.
and GPIOi.
).
•
Synchronous interrupt request line 1 is mapped on the MPU INTC.
•
Synchronous interrupt request line 2 is mapped on the IVA2.2 INTC.
lists the interrupt lines that are driven out from the general-purpose interface to the MPU INTC
and the IVA2.2 INTC.
Table 25-3. Interrupts
Name
Mapping
Comments
GPIO1
GPIO1_MPU_IRQ
M_IRQ_29
Destination is the MPU INTC.
GPIO1_IVA2_IRQ
IVA2_IRQ[28]
Destination is the IVA2.2 INTC.
GPIO2
GPIO2_MPU_IRQ
M_IRQ_30
Destination is the MPU INTC.
GPIO2_IVA2_IRQ
IVA2_IRQ[29]
Destination is the IVA2.2 INTC.
GPIO3
GPIO3_MPU_IRQ
M_IRQ_31
Destination is the MPU INTC.
GPIO3_IVA2_IRQ
IVA2_IRQ[30]
Destination is the IVA2.2 INTC.
GPIO4
GPIO4_MPU_IRQ
M_IRQ_32
Destination is the MPU INTC.
GPIO4_IVA2_IRQ
IVA2_IRQ[31]
Destination is the IVA2.2 INTC.
GPIO5
GPIO5_MPU_IRQ
M_IRQ_33
Destination is the MPU INTC.
GPIO5_IVA2_IRQ
IVA2_IRQ[32]
Destination is the IVA2.2 INTC.
GPIO6
GPIO6_MPU_IRQ
M_IRQ_34
Destination is the MPU INTC.
GPIO6_IVA2_IRQ
IVA2_IRQ[43]
Destination is the IVA2.2 INTC.
25.3.1.2.1.1 Wake-Up Generation
GPIO1 of the general-purpose interface is attached to the WKUP power domain (see
, Power,
Reset, and Clock Management) and can wake up the system.
NOTE:
GPIO2 to GPIO6 modules belong to the PER power domain and thus have wake-up system
capability only when the PER power domain is active.
3473
SWPU177N – December 2009 – Revised November 2010
General-Purpose Interface
Copyright © 2009–2010, Texas Instruments Incorporated
