Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 3465 / 3738

GPIO6
Device
Debounce clock
MPU subsystem
interrupt
controller
PRCM
IVA2.2 subsystem
interrupt
controller
L4-Per
interconnect
Interface clock
Interrupt requests
Interrupt requests
Wake-up
requests
GPIO
GPIO2_MPU_IRQ
GPIO2_IVA2_IRQ
GPIO2_WAKE
other GPIO modules
(GPIO3 to GPIO6)
GPIO2_DBCLK
6
6
GPIO3
GPIO4
GPIO 5
GPIO2_ICLK
General-purpose interface
GPIO 1
GPIO1_MPU_IRQ
GPIO1_IVA2_IRQ
GPIO1_DBCLK
GPIO1_ICLK
gpio_[31:0]
GPIO1_WAKE
L4-Wake-up
interconnect
6
GPIO_[31:0]
GPIO_[186:160]
_
GPIO_[159:128]
GPIO_[126:96]
GPIO_[95:64]
GPIO_[63:34]
DAC1
GPIO_33
TV_DETECT
GPIO_[191:188]
gpio_[191:188]
BANDGAP
GPIO_[127]
TSHUT
gpif-001
2
gpio_[186:160]
gpio_[159:128]
gpio_[127]
gpio_[126:96]
gpio_[95:64]
gpio_[63:34]
Public Version
www.ti.com
General-Purpose Interface Overview
Figure 25-1. General-Purpose Interface Overview
Each channel in GPIOs has the following features:
•
The GPIOi. GPIO_OE register controls the output capability for each pin.
• The output line level reflects the value written in the GPIOi. GPIO_DATAOUT register through the level
4 (L4) interconnect.
• The input line can be fed to GPIO through an optional and configurable debounce cell. (The
debouncing time value is global for all ports of one GPIO module, so up to five different debouncing
time values are possible.)
• The input line value is sampled into the GPIOi. GPIO_DATAIN register and can be read through the L4
interconnect.
• In active mode, the input line can be used through level and edge detectors to trigger synchronous
interrupts. The edge (rising, falling, or both) or the level (logical 0, logical 1, or both) used can be
configured.
• In idle mode, the input line can be used to activate the asynchronous wake-up request (on edge
detection: Rising edge, falling edge, or both).
The module provides an alternative to the atomic test and set operations for the following registers:
•
GPIOi. GPIO_DATAOUT
• GPIOi. GPIO_IRQENABLE1
• GPIOi. GPIO_IRQENABLE2
• GPIOi. GPIO_WAKEUPENABLE
For these registers, the modules implement the set-and-clear protocol register update (see
Section 25.5.2 , Set and Clear Instructions).
3465 SWPU177N – December 2009 – Revised November 2010 General-Purpose Interface
Copyright © 2009–2010, Texas Instruments Incorporated