Texas Instruments OMAP36 Series, Technical Reference Manual

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MMC/SD/SDIO Register Manual
Bits Field Name Description Type Reset
17:16 Reserved Reserved bit field. Do not write any value R 00
The value of these bits after soft reset is 0x0. These bits will be
automatically set to 0x3 after debounce time.
Debounce time is fixed to 256 x32 kHz clock cycles.
15:12 Reserved Reserved bit field. Do not write any value R 0x0
11 BRE Buffer read enable. R 0
This bit is used for non-DMA read transfers. It indicates that a complete
block specified by MMCi.
MMCHS_BLK [10:0] BLEN bits has been written in
the buffer and is ready to be read.
It is set to 0 when the entire block is read from the buffer. It is set to 1
when a block data is ready in the buffer and generates the Buffer read
ready status of interrupt (MMCi.
MMCHS_STAT [5] BRR bit).
Read 0x0: Read BLEN bytes disable
Read 0x1: Read BLEN bytes enable. Readable data exists in the
buffer.
10 BWE Buffer Write enable. R 0
This status is used for non-DMA write transfers. It indicates if space is
available for write data.
Read 0x0: There is no room left in the buffer to write BLEN bytes of
data.
Read 0x1: There is enough space in the buffer to write BLEN bytes of
data.
9 RTA Read transfer active. R 0
This status is used for detecting completion of a read transfer. It is set to 1
after the end bit of read command or by activating a continue request
(MMCi.
MMCHS_HCTL [17] CR bit) following a stop at block gap request.
This bit is set to 0 when all data have been read by the local host after last
block or after a stop at block gap request.
Read 0x0: No valid data on the mmci_dat lines.
Read 0x1: Read data transfer on going.
8 WTA Write transfer active. R 0
This status indicates a write transfer active. It is set to 1 after the end bit of
write command or by activating a continue request
(MMCi.
MMCHS_HCTL [17] CR bit) following a stop at block gap request.
This bit is set to 0 when CRC status has been received after last block or
after a stop at block gap request.
Read 0x0: No valid data on the mmci_dat lines.
Read 0x1: Write data transfer on going.
7:3 Reserved Reserved bit field. Do not write any value R 0x00
2 DLA mmci_dat line active. R 0
This status bit indicates whether one of the mmci_dat line is in use. In the
case of read transactions (card to host):
This bit is set to 1 after the end bit of read command or by activating
continue request MMCi.
MMCHS_HCTL [17] CR bit. This bit is set to 0 when
the host controller received the end bit of the last data block or at the
beginning of the read wait mode. In the case of write transactions (host to
card):
This bit is set to 1 after the end bit of write command or by activating
continue request MMCi.
MMCHS_HCTL [17] CR bit.
This bit is set to 0 on the end of busy event for the last block; host
controller must wait 8 clock cycles with line not busy to really consider not
"busy state" or after the busy block as a result of a stop at gap request.
Read 0x0: mmci_dat Line inactive
Read 0x1: mmci_dat Line active
1 DATI Command inhibit (mmci_dat). R 0
This status bit is generated if either mmci_dat line is active
(MMCi.
MMCHS_PSTATE [2] DLA bit) or Read transfer is active
(MMCi. MMCHS_PSTATE [9] RTA bit) or when a command with busy is
issued. This bit prevents the local host to issue a command.
A change of this bit from 1 to 0 generates a transfer complete interrupt
(MMCi.
MMCHS_STAT [1] TC bit).
Read 0x0: Issuing of command using the mmci_dat lines is allowed
3443 SWPU177N – December 2009 – Revised November 2010 MMC/SD/SDIO Card Interface
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