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MMC/SD/SDIO Integration
•
The MMCi.
[26] SRD bit resets all finite state-machines and status management that
handle data transfers on both the interface and functional side.
•
The MMCi.
[25] SRC bit resets all finite state-machines and status management that
handle command transfers on both the interface and functional side.
24.3.1.3 Power Domain
MMC/SD/SDIOi power is supplied by the CORE power domain (see
, Power Reset and Clock
Management for more information).
When the MMC/SD/SDIOi power domain is off, the only way to wake up the power domain and different
MMC/SD/SDIOi clocks is to monitor mmci_dat[1] input pin state via a different GPIO line for each
MMC/SD/SDIO interface (see
, General-Purpose Interface, for more information).
24.3.2 Hardware Requests
24.3.2.1 DMA Requests
The MMC/SD/SDIOi host controller can be interfaced with a DMA controller. At system level, the
advantage is to discharge the LH of the data transfers. The module does not support wide DMA access
(above 1024 bytes) for SD cards as specified in the SD Card Specification, Part A2, SD Host Controller
Standard Specification, v1.00.
The DMA request is issued if the three following conditions are met:
•
The MMCi.
[0] DE bit is set to 1 to trigger the initial DMA request (the write must be done
when running the data transfer command).
•
A command was emitted on the mmci_cmd line.
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There is enough space in the buffer of the MMC/SD/SDIOi host controller to write an entire block
(BLEN writes).
DMA request lines are connected on the system DMA (sDMA) inputs:
•
S_DMA_60 (MMC1_DMA_TX)
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S_DMA_61 (MMC1_DMA_RX)
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S_DMA_46 (MMC2_DMA_TX)
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S_DMA_47 (MMC2_DMA_RX)
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S_DMA_76 (MMC3_DMA_TX)
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S_DMA_77 (MMC3_DMA_RX)
24.3.2.1.1 DMA Receive Mode
In a DMA block read operation (single or multiple), the request signal MMCi_DMA_RX is asserted to its
active level when a complete block is written in the buffer. The block size transfer is specified in the
MMCi.
[10:0] BLEN field.
The MMCi_DMA_RX signal is deasserted to its inactive level when the sDMA has read one single word
from the buffer.
Only one request is sent per block; the DMA controller can make a 1-shot read access or several DMA
bursts, in which case the DMA controller must manage the number of burst accesses, according to block
size BLEN field.
New DMA requests are internally masked if the sDMA has not read exactly BLEN bytes and a new
complete block is not ready. As DMA accesses are in 32-bit, then the number of sDMA read is
Integer(BLEN/4)+1.
The receive buffer never overflows. In multiple block transfers for block size above 512 bytes, when the
buffer gets full, the mmci_clk clock signal (provided to the card) is momentarily stopped until the sDMA or
the MPU performs a read access, which reads a complete block in the buffer.
Summary (see
•
DMA transfer size = BLEN buffer size (maximum 1024 32-bit words) in one shot or by burst
3379
SWPU177N – December 2009 – Revised November 2010
MMC/SD/SDIO Card Interface
Copyright © 2009–2010, Texas Instruments Incorporated
