prcm-042
CM
Clock generator
MPU core
DPLL1
PRM
CORE power domain
MPU power domain
DPLL1_ALWON_FCLK
L3_ICLK
MPU subsystem
MPU INTC
DPLL1_FCLK
WKUP power domain
CORE power domain
MPU_CLK
Asynchronous
bridge - slave
Asynchronous
bridge - master
DPLL1 power domain
Public Version
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PRCM Functional Description
3.5.3.4
Clock Distribution
3.5.3.4.1 Power Domain Clock Distribution
This section describes the PRCM clock distribution over device power domains.
3.5.3.4.1.1 MPU Power Domain
The PRCM module does not directly provide any clock to the MPU power domain. It feeds only DPLL1,
which generates MPU_CLK. All clocks are then locally generated by the clock generator in the MPU
subsystem.
shows the clocking scheme in the MPU power domain.
Figure 3-45. MPU Power Domain Clocking Scheme
NOTE:
ARM_FCLK is sourced by MPU_CLK and has the same frequency. (For more information
about ARM_FCLK, see
, MPU Subsystem).
3.5.3.4.1.2 IVA2 Power Domain
The PRCM module does not directly provide any clock to the IVA2 power domain. It feeds only DPLL2,
which generates IVA2_CLK. All clocks are then locally generated by a clock generator in the IVA2.2
subsystem.
shows the clocking scheme in the IVA2 power domain.
309
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
