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McSPI Register Manual
Table 20-46. MCSPI_XFERLEVEL
Address Offset
0x7C
Physical Address
0x4809 807C
Instance
MCSPI1
0x4809 A07C
MCSPI2
0x480B 807C
MCSPI3
0x480B A07C
MCSPI4
Description
This register provides transfer levels needed while using FIFO buffer during transfer.
Type
RW
Write Latency
Immediate
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WCNT
AFL
AEL
Reserved
Reserved
Bits
Field Name
Description
Type
Reset
31:16
WCNT
Spi word counter: This register holds the programmable value of
RW
0x0000
number of SPI word to be transferred on channel which is using
the FIFO buffer. When transfer had started, a read back in this
register returns the current SPI word transfer index.
0x0:
Counter not used
0x1:
One spi word
0xFFFE 65534 spi word
:
0xFFFF 65535 spi word
:
15:14
Reserved
Read returns 0s.
RW
0x0
13:8
AFL
Buffer Almost Full: This register holds the programmable almost
RW
0x00
full level value used to determine almost full buffer condition. If the
user wants an interrupt or a DMA read request to be issued
during a receive operation when the data buffer holds at least I
bytes, then this bit field must be set to I-1.
0x0:
One byte
0x1:
2 bytes
0x3E:
63 bytes
0x3F:
64 bytes
7:6
Reserved
Read returns 0s.
RW
0x0
5:0
AEL
Buffer Almost Empty: This register holds the programmable
RW
0x00
almost empty level value used to determine almost empty buffer
condition. If the user wants an interrupt or a DMA write request to
be issued during a transmit operation when the data buffer is able
to receive I bytes, then this bit field must be set to I-1.
0x0:
One byte
0x1:
2 bytes
0x3E:
63 bytes
0x3F:
64 bytes
3053
SWPU177N – December 2009 – Revised November 2010
Multichannel SPI
Copyright © 2009–2010, Texas Instruments Incorporated