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UART/IrDA/CIR Overview
•
Baud rate = (functional clock/16)/N
•
Baud rate = (functional clock/13)/N
This software programming mode enables higher baud rates with the same error amount without changing
the clock source:
•
Break character detection and generation
•
Configurable data format
–
Data bit: 5, 6, 7, or 8 bits
–
Parity bit: Even, odd, none
–
Stop-bit: 1, 1.5, 2 bit(s)
•
Flow control: Hardware (RTS/CTS) or software (XON/XOFF) (UART1, UART2 and UART3 only)
The UART clocks are connected to produce a baud rate of up to 3.6M bits/s.
lists the
supported baud rates, the requested divisor, and the corresponding error versus the standard baud rate.
Table 19-1. UART Mode Baud Rates, Divisor Values, and Error Rates
Baud Rate
Oversampling
Divisor
Error (%)
300
16
10000
0
600
16
5000
0
1200
16
2500
0
2400
16
1250
0
4800
16
625
0
9600
16
312
0.16
14,400
16
208
0.16
19,200
16
156
0.16
28,800
16
704
0.16
38,400
16
78
0.16
57,600
16
52
0.16
115,200
16
26
0.16
230,400
16
13
0.16
460,800
13
8
0.16
921,600
13
4
0.16
1,843,200
13
2
0.16
3,000,000
16
1
0
3,686,400
13
1
0.16
19.1.2 IrDA Features
The IrDA (UART3 only) includes the following key features:
•
Support of IrDA 1.4 slow infrared (SIR), medium infrared (MIR), and fast infrared (FIR) communications
–
Frame formatting: Addition of variable beginning-of-frame (xBOF) characters and end-of-frame
(EOF) characters
–
Uplink/downlink cyclic redundancy check (CRC) generation/detection
–
Asynchronous transparency (automatic insertion of break character)
–
Eight-entry status FIFO (with selectable trigger levels) to monitor frame length and frame errors
–
Framing error, CRC error, illegal symbol (FIR), and abort pattern (SIR, MIR) detection
lists the supported baud rates, the requested divisor, and the corresponding error versus the
standard baud rate.
2871
SWPU177N – December 2009 – Revised November 2010
UART/IrDA/CIR
Copyright © 2009–2010, Texas Instruments Incorporated
