Texas Instruments OMAP36 Series, Technical Reference Manual

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I2C i
i2c _scl
i
(where = 1, 2, 3
and i2c _sccbe is not available for I2C1) i
i
i2c _sda i
i2c _sccbe i
i2c-012
Device
Public Version
HS I
2
C Environment
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Figure 17-12. HS I
2
C Controller Interface Signals in SCCB Mode
17.2.2.2 HS I
2
C SCCB Interface Typical Connections
Table 17-2 lists the pins associated with the SCCB interface.
Table 17-2. HS I
2
C Input/Output
Signal I/O
(1)
Description Reset Value I2Ci. I2C_CON [15]
I2C_EN = 0
i2ci_scl O SCCB serial clock line
(2)
. Standard CMOS output Hi-Z High
buffer.
i2ci_sda I/O(OD) SCCB serial data line. Standard CMOS 3-state output Hi-Z Hi-Z
buffer. Requires external conflict-protection resistor for
each slave device connected to the bus.
i2ci_sccbe
(3)
O SCCB enable line. Standard CMOS output buffer. High High
(1)
I = Input; O = Output; OD = Open Drain; Hi-Z = High Impedance
(2)
This output signal is also used as retiming input.
(3)
This signal is used for the 3-wire SCCB protocol only.
NOTE: Because they share the same ball, the i2c2_sccbe and i2c3_sccbe signals are not available
at the same time. For detailed information about pin configuration, see Chapter 13 , System
Control Module.
The HS I
2
C1 module does not provide any i2c1_sccbe signal at the chip boundary of the
device; thus, this module does not support the 3-wire SCCB protocol.
2776 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated