Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 2770 / 3738

Device +1.8 V
I C-1.8 V
2
compatible
device
I2C i
where = 1, 2, 3 i
i2c _scl i
i2c _sda i
Pullup resistors (Rp)
I C-1.8 V
2
compatible
device
I C-3.0 V
2
compatible
device
I C-3.0 V
2
compatible
device
Serial
clock
line
i
Serial
data
line
i
+3.0 V
i2c-002
I2C i
where = 1, 2, 3 i
i2c _scl i
i2c _sda i
i2c-003
Device
Public Version
HS I
2
C Environment
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17.2 HS I
2
C Environment
17.2.1 HS I
2
C in I
2
C Mode
Figure 17-2 shows the HS I
2
C controllers and their related connections with I
2
C-compliant devices in I
2
C
mode.
Figure 17-2. HS I
2
C Controllers and Typical Connections to I
2
C Devices
17.2.1.1 HS I
2
C Pins for Typical Connections in I
2
C Mode
Figure 17-3 shows the HS I
2
C controllers pins used for typical connections with I
2
C devices.
Figure 17-3. HS I
2
C Controller Interface Signals in I
2
C Mode
17.2.1.2 HS I
2
C Interface Typical Connections
Table 17-1 lists the pins associated with the I
2
C interface.
Table 17-1. HS I
2
C Input/Output
Signal I/O
(1)
Description Reset Value
i2ci_scl I/O(OD) I
2
C serial clock line
(2)
. Open-drain output buffer. Requires Hi-Z for i=1; 1 for i=2,3
external pullup resistor (Rp).
i2ci_sda I/O(OD) I
2
C serial data line. Open-drain output buffer. Requires Hi-Z for i=1; 1 for i=2,3
external Rp.
(1)
I = Input; O = Output; OD = Open Drain; Hi-Z = High Impedance
(2)
This signal is also used as retiming input.
2770 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated