Texas Instruments OMAP36 Series, Technical Reference Manual

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General-Purpose Timers
The dedicated output pin (timer PWM) can be programmed in the GPTi. TCLR [12] PT bit through the
GPTi. TCLR [11:10] TRG field to generate one positive pulse (timer clock duration) or to invert the current
value (toggle mode) when an overflow or a match occurs.
16.2.4.5 Prescaler Functionality
A prescaler can be used to divide the timer counter input clock frequency. The prescaler is enabled when
the GPTi.
TCLR [5] PRE bit is set. The GPTi. TCLR [4:2] PTV field sets the second prescaler ratio. The
prescaler counter is reset when the timer counter is stopped or reloaded on-the-fly.
Table 16-9 lists the prescaler/timer reload values versus contexts.
Table 16-9. Prescaler/Timer Reload Values Versus Contexts
Context Prescaler Timer Counter
Overflow (when autoreload is on) Reset GPTi. TLDR [31:0]
TCRR write Reset GPTi. TCRR [31:0]
TTGR write Reset GPTi. TLDR [31:0]
Stop Reset Frozen
16.2.4.6 Pulse-Width Modulation
The timer can be configured to provide a programmable PWM output. The timer PWM output pin can be
configured to toggle on an event. The GPTi.
TCLR [11:10] TRG field determines on which register value the
PWM pin toggles. Either overflow alone or both overflow and match can be selected to toggle the timer
PWM pin when a compare condition occurs.
CAUTION
In toggle mode when GPTi. TCLR [11:10] TRG = 0x2 (overflow and match), the
first event that will toggle the PWM line is an overflow event. If a match event
occurs first, it will not toggle the PWM line.
Figure 16-13 illustrates those.
The GPTi. TCLR [7] SCPWM bit can be programmed to set or clear the timer PWM output signal only while
the counter is stopped or the trigger is off. This allows setting the output pin to a known state before
modulation starts. Modulation synchronously stops when the GPTi.
TCLR [11:10] TRG field is cleared and
overflow occurs. This allows fixing a deterministic state of the output pin when modulation stops.
In Figure 16-12 , the internal overflow pulse is set each time (0xFFFF FFFF - GPTi. TLDR [31:0]
LOAD 1) the value is reached, and the internal match pulse is set when the counter reaches the
GPTi.
TMAR register value. According to the value of the GPTi. TCLR [12] PT and GPTi. TCLR [11:10] TRG
bits, the timer provides pulse or PWM event on the output pin (timer PWM).
The GPTi. TLDR and GPTi. TMAR registers must keep values smaller than the overflow value (0xFFFF
FFFF) by at least two units. In case the PWM trigger events are both overflow and match, the difference
between the values kept in the GPTi.
TMAR register and the value in the GPTi. TLDR register must be at
least two units. When match event is used, the compare mode GPTi. TCLR [6] CE bit must be set.
In Figure 16-12 , the GPTi. TCLR [7] SCPWM bit is set to 0. In Figure 16-13 , the GPTi. TCLR [7] SCPWM bit
is set to 1. To obtain the desired wave form, start the counter at 0xFFFF FFFE value (to ensure an
overflow first) or adjust the line polarity (GPTi.
TCLR [7] SCPWM bit).
2719 SWPU177N – December 2009 – Revised November 2010 Timers
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