timers-008
Load register
(TLDR)
Counter register
(TCRR)
0xFFFF FFFF
Overflow
reset pulse is
generated.
Trigger register
(TTGR)
0x0000 0000
Public Version
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General-Purpose Timers
CAUTION
Do not put the overflow value (0xFFFFFFFF) in the GPTi.
register
because it can lead to undesired results.
An interrupt can be issued on overflow if the overflow interrupt enable bit is set in the timer interrupt
enable register (GPTi.
[1] OVF_IT_ENA bit set to 1), the interrupt is enabled after 10 * GPTi.ICLK
clock cycles. A dedicated output pin (timer PWM) can be programmed in GPTi.
[12] through
[11:10] (PT and TRG bits) to generate one positive pulse (prescaler duration) or to invert the
current value (toggle mode) when an overflow occurs. The GPTi.
[12] PT bit selects pulse/toggle
modulation (GPTi.
[11:10] TRG bit field select trigger mode).
shows the GPTi.
timing value.
Figure 16-8. GPTi.TCRR Timing Value
16.2.4.2.1 1-ms Tick Generation (Only GPTIMER1, GPTIMER2, and GPTIMER10)
Because the timer input clock is 32,768 Hz, the interrupt period is not exactly 1 ms. If the clock counts up
to 32, it obtains a 0.977-ms period; if it counts up to 33, it obtains a 1.007-ms period. For large granularity,
the error is cumulative and can generate important deviations to the standard value.
To minimize the error between a true 1-ms tick and the tick generated by the 32,768 Hz timer, the
sequencing of periods less than 1 ms and periods greater than 1 ms must be shuffled. An additional 1-ms
block is used to correct this error. Refer to
In this implementation, the increment sequencing is automatically managed by the timer to minimize the
error. The user must define only the value of the timer positive increment register (GPTi.
[31:0]
POSITIVE_INC_VALUE bit field) and the timer negative increment register (GPTi.
NEGATIVE_INC_VALUE bit field). An automatic adaptation mechanism is used to simplify the
programming model.
2715
SWPU177N – December 2009 – Revised November 2010
Timers
Copyright © 2009–2010, Texas Instruments Incorporated
