MMU-017
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MMU Functional Description
Figure 15-17. TLB Entry Structure
15.3.5 MMU Error Handling
The following types of faults can occur:
•
TLB miss with table walker disabled
No translation is found for the virtual address required. If the hardware table walker is disabled, a fault
is generated.
•
Translation fault
No translation is found for the virtual address required (TLB miss). The table walker is enabled but a
page table entry does not exist for the given virtual address.
•
Table walk fault
A table walk results in a memory read error.
•
Multi-hit fault
More than one valid entry exists in the TLB for the given virtual address.
When a fault occurs and its corresponding interrupt is enabled, an interrupt is signaled to the MPU. The
interrupt service routine (ISR) is then responsible for fault recovery. The requestor is stalled by the MMU
while the fault is handled. For example, for a TLB miss, the ISR might load the missing entry into the TLB.
The ISR can determine the cause of the fault interrupt by reading the MMUn.
register.
The virtual address that caused the fault can be determined by reading the MMUn.
register.
In the case of a TLB miss, the MMU continues servicing the request as soon as a valid TLB entry is
written. In the case of a translation fault, table walk fault, or mult-hit fault, the ISR first addresses the
cause of the fault and then releases the MMU by writing to the interrupt status register. The MMU then
continues servicing the request.
15.3.6 MMU Instance Design Parameters
The various MMU instances have different design parameters, most notably the size of the virtual address
space and the number of TLB entries.
shows the correspondence between the MMU instances
and the design parameters.
2679
SWPU177N – December 2009 – Revised November 2010
Memory Management Units
Copyright © 2009–2010, Texas Instruments Incorporated
