Public Version
SCM Programming Model
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CAUTION
The following are critical requirements for the cell:
•
The VMODE bit must be defined before the PWRNDZ bit is made HIGH
(cell is brought out of PWRNDZ).
•
The default state of VMODE bit must be HIGH (to indicate 3.0-V operation).
•
PWRNDZ bit must be kept LOW when the SDMMC1_VDDS/SIM_VDDS
supply is ramping up (PWRNDZ bit is not required to be kept LOW during
ramp down of the supply). This could be damaging.
CAUTION
It
is
strongly
recommended
to
synchronize
any
changes
of
the
PBIASLITEPWRDNZ1 and GPIO_IO_PWRDNZ bits (that is, both bits must be
set to 1 or 0 at the same time).
The following power-saving recommendations apply to the power-down mode control PWRDNZx (the
PBIASLITEPWRDNZ0/PBIASLITEPWRDNZ1 and GPIO_IO_PWRDNZ bits) and the pad configuration
settings for different SDMMC1/GPIO pad setups:
•
When SDMMC1 (or GPIO) I/Os are used with SDMMC1 (or GPIO) functionality and vdds_sdmmc1 (or
vdds_sim) = vdds = 1.8 V, the corresponding PWRDNZx bit(s) must be set to 1 when the
vdds_sdmmc1 (or vdds_sim) power supply voltage is stabilized.
•
When SDMMC1 (or GPIO) I/Os are not connected and vdds_sdmmc1 (or vdds_sim) = 0 V, the
corresponding PWRDNZx bit(s) must be set to 0.
•
When SDMMC1 (or GPIO) I/Os are not connected and vdds_sdmmc1 (or vdds_sim) = 1.8 V, one of
the following settings can be done to reduce leakage:
–
The corresponding PWRDNZx bit(s) is kept at 0.
–
If the corresponding PWRDNZx bit(s) is 1, the INPUTENABLE bit must be maintained at 0 in the
corresponding CONTROL_PADCONF_x register. In this case, the receiver buffer does not cause
static current, even if the pad is left floating. Weak pullup/pulldown resistors can be used to define
the pad state, if needed. The setting of the weak pull resistor does not affect the I/O leakage in this
case.
–
If the corresponding PWRDNZx bit(s) must be kept at 1 and INPUTENABLE = 1, the level of the
pad signal must be defined using weak pullup/pulldown resistors at the pad, in the event of a
floating pad. If weak pull resistors are not defined and the pad is floating, the current, drawn from
VDDS, can be high because of the static current in the receiver.
For more information about power-saving strategies related to pad configuration, see
, Pad
Configuration Programming Points.
13.5.2.1 PBIAS Error Generation
summarizes the generation of the PBIAS error interrupt (PBIAS0_ERROR and
PBIAS1_ERROR) depending on the various CONTROL.
bits control. The shaded
row is a potential condition that could cause a reliability issue if not detected. To prevent this reliability
issue, the PBIAS voltage is kept at SDMMC1_VDDS/SIM_VDDS level when the PBIAS error signal is
HIGH.
Table 13-68. PBIAS Error Signal Truth Table
VMODE
PWRDNZ
SUPPLY_HIGH
PBIAS ERROR
X
X
X
0
0
0
X
0
0
1
0
0
0
1
1
1
2538System Control Module
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
