Texas Instruments OMAP36 Series, Technical Reference Manual

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MPU subsystem
MPU_INTC_FCLK
MPU
PRCM
MPU_INTC_RST
MPU INTCPS
MPU_INTC_FIQ
M_IRQ_[95:0]
MPU_INTC_IRQ
Local
interconnect
Device
modules
MPU DPLL DPLL1_FCLK
CORE_RST
96
intc-003
sys_nirq
Public Version
www.ti.com
MPU Subsystem INTCPS Integration
12.3 MPU Subsystem INTCPS Integration
The INTCPS module is the interface between incoming interrupts and the two interrupt inputs of the MPU.
It can handle up to 96 request inputs that can be configured as MPU FIQ or IRQ interrupt requests.
Figure 12-3 shows the integration of the INTCPS in the MPU subsystem.
Figure 12-3. MPU Subsystem INTCPS Integration
The MPU subsystem INTCPS is directly connected to the MPU by an MPU peripheral port. Consequently,
the MPU subsystem INTCPS is accessible and visible only by the MPU.
12.3.1 Clocking, Reset, and Power Management Scheme
12.3.1.1 MPU Subsystem INTC Clocks
The MPU subsystem INTCPS runs at half the rate of the MPU functional clock (see Chapter 4 , MPU
Subsystem).
The interface clock used for register access runs at the rate of the interconnect bus clock (equal to the
rate of the MPU interface clock; see
Chapter 3 , Power, Reset, and Clock Management).
The synchronizer clock allows external asynchronous interrupts to be resynchronized before they are
masked.
Table 12-1 lists the MPU subsystem INTC clock rates.
Table 12-1. MPU Subsystem INTC Clock Rates
Clock Frequency Name Comments
Functional ARM_FCLK MPU_INTC_FCLK Source is the MPU DPLL.
Interface ARM_FCLK MPU_INTC_ICLK Source is the PRCM module.
Synchronizer MPU_INTC_FCLK Synchronizer clock Source is the MPU_INTC_FCLK.
(module internal
clock)
2407 SWPU177N – December 2009 – Revised November 2010 Interrupt Controller
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