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SDMA Functional Description
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11.4.19.4.6 Stop a Linked List (Abort or Drain)
The channel can be stopped in case of a drain or an abort. These cases are exclusive.
11.4.19.4.6.1 Drain
•
Drain conditions:
A channel is a drain candidate if it is a hardware-source-synchronized transfer with
BUFFERING_DISABLE = 0 and channel should not be doing any of the graphics operation
(transparent copy or solid-color fill).
•
Drain trigger:
A drain candidate channel is drained if it is disabled. (
[7] ENABLE = 0) or if it receives a
transaction error on the read port.
•
Drain behavior with a type 1, 2, or 3 descriptor. Drain trigger can occur in two situations:
–
During descriptor loading: Any ongoing current transaction is complete and the channel is aborted.
–
During data loading: The read is completed at the boundary of the request
(element/frame/packet/block boundary), the FIFO is drained to the destination, and then a
DRAIN_END interrupt can be asserted.
11.4.19.4.6.2 Abort
•
Abort condition:
A channel is an abort candidate if it is software-synchronized, hardware-destination-synchronized, solid
color-fill, transparent-color fill, or hardware-source-synchronized with
BUFFERING_DISABLE = 1.
•
Abort trigger:
A channel is an abort candidate if it is disabled. (
[7] ENABLE = 0), if it receives a
transaction error on the read or write port, or if there is a MISALIGNMENT_ERROR.
•
Abort behavior with a type 1, 2, or 3 descriptor:
If an abort trigger occurs, the channel aborts immediately after completion of current read/write
transactions and then the FIFO is cleaned up.
In type 1, 2, or 3, if an abort trigger or drain trigger occurs during the descriptor load phase, the
channel aborts.
11.4.19.4.7 Status Bit Behavior
This section describes the behavior of the
[6] SYNC,
[9] RD_ACTIVE and
[10] WR_ACTIVE status bits:
•
For a hardware-synchronized channel in linked-list mode, the
[6] SYNC bit becomes
active (
[6] SYNC = 1) when the first data load transaction is scheduled and remains active
until the last data load transaction in the block (not super block) is descheduled (
[6] SYNC
= 0). The SYNC bit is not active during the descriptor load phase.
•
The
[9] RD_ACTIVE bit is active during the data load phase and the descriptor load
phase. It becomes active when the first read transaction is scheduled. It becomes inactive:
–
When (during the descriptor load phase) the last descriptor write request is descheduled
–
When (during the data load phase) the last read transaction in the block (not super block) is
descheduled for software-synchronized transfer or destination-synchronized transfer with prefetch
enabled
–
When (during the data load phase) the last read transaction in the request
(element/frame/packet/block sync) is descheduled for hardware-source-synchronized transfer or
hardware-destination-synchronized transfer without prefetch
•
The
[10] WR_ACTIVE bit is active only during the data load phase. It becomes active
when the first write transaction is scheduled and becomes inactive:
–
Until the last write transaction in the block (not super block) is descheduled and the FIFO is cleaned
up for software-synchronized transfer
–
Until the last write transaction in the request (element/frame/packet/block sync) is descheduled and
the FIFO is cleaned up for hardware-source-synchronized transfer (with
[25]
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SDMA
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated