DMA request asserted
dma-002
First DMA access accepted
DMA request asserted
dma-003
Public Version
SDMA Integration
www.ti.com
Figure 11-3. Edge-Sensitive DMA Request Scheme
For a transition-sensitive DMA request (see
), the line must be maintained low (asserted) until
the first DMA access is complete, after which the line must be maintained high (deasserted) for greater
than one clock cycle (CORE_L3_ICLK).
When the deassertion time is less than one clock cycle, the SDMA might not detect the deassertion.
When the channel is enabled one cycle after a DMA request is disabled, the channel detects the DMA
request and starts the corresponding transfer.
When the channel is enabled two cycles after the DMA request is disabled, the channel does not detect
the DMA request.
Figure 11-4. Transition-Sensitive DMA Request Scheme
11.3 SDMA Integration
highlights the SDMA controller integration.
2340
SDMA
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
