Public Version
SDMA Overview
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11.1 SDMA Overview
The system direct memory access (SDMA), also called DMA4, performs high-performance data transfers
between memories and peripheral devices without microprocessor unit (MPU) or digital signal processor
(DSP) support during transfer. A DMA transfer is programmed through a logical DMA channel, which
allows the transfer to be optimally tailored to the requirements of the application.
The device also embeds dedicated DMA controllers: the camera image signal processor (ISP) DMA; the
enhanced DMA (EDMA), which is embedded in the IVA2.2 subsystem; the display DMA; and the universal
serial bus (USB) high-speed (HS) DMA. For more information, see
, Camera ISP Subsystem;
, IVA Subsystem;
, Display Subsystem; and
, High-Speed USB Controllers.
The DMA controller includes the following main features:
•
Data transfer support in either direction between:
–
Memory and memory
–
Memory and peripheral device
•
32 logical DMA channels supporting:
–
Multiple concurrent transfers
–
Independent transfer profile for each channel
–
8-bit, 16-bit, or 32-bit data element transfer size
–
Software-triggered or hardware-synchronized transfers
–
Flexible source and destination address generation
–
Burst read and write
–
Chained multiple-channel transfers
–
Endianism conversion
–
Draining
–
Linked-list support for descriptor types 1, 2, and 3
•
First-come, first-serve DMA scheduling with fixed priority
•
Up to 96 DMA requests
•
Constant fill
•
Transparent copy
•
Four programmable interrupt request output lines
•
FIFO depth: 256 x 32-bits
•
Data buffering
•
FIFO budget allocation
•
Power-management support
•
Auto-idle power-saving support
•
Implementation of retention flip-flops (RFFs) to support dynamic power saving (DPS) between system
power modes without MPU involvement
shows an overview of the SDMA module.
2336
SDMA
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated