Configuration port
SDMA_IRQ_0
SDMA_IRQ_1
SDMA_IRQ_2
SDMA_IRQ_3
SDMA controller
Read port
S_DMA_[95:0]
MPU INTC
OMAP3430
L3/L4 system
peripherals
Device
peripherals
Write port
sys_ndmareq[3:0]
L4-Core interconnect
Device
SDMA_FCLK
PRCM
dma-001
IVA2.2 INTC
L3 interconnect
SDMA_ICLK
SDMA_RST
L3 functional/interface clock
L4 interface clock
Reset
STANDBY/IDLE
hardware handshake
DMA requests
IVA2.2 subsystem
MPU subsystem
Memory subsystem
L4 interconnect
L4
peripherals
Public Version
www.ti.com
SDMA Overview
Figure 11-1. SDMA Overview
The SDMA module has three ports - one read, one write and one configuration port - and provides
multiple logical channel support. A dynamically allocated FIFO queue memory pool provides buffering
between the read and write ports. Read and write ports are multithreaded (two threads for the write port
and four threads for the read port); this means that each transaction is flagged by a thread ID (0, 1, 2, or
3) in the request direction and in the response direction. This allows the read port to have four outstanding
requests at a time. The write port has two threads budget available.
The MPU (or DSP) configures the SDMA controller through the L4-Core interconnect.
2337
SWPU177N – December 2009 – Revised November 2010
SDMA
Copyright © 2009–2010, Texas Instruments Incorporated