FCLK
Data capture on GPMC side: RdAccessTime = 9
nADV
AdvRdOffTime = 1
RdCycleTime = 11
nCS
nOE
Valid Address
A/D bus
CsReadOffTime = 10
OeOffTime = 10
OeOnTime = 3
Data Setup time
Data Hold time
tOEZ
Valid Address
DATA
Memory-side access time
gpmc-039
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General-Purpose Memory Controller
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cycle time.
•
Addresses can now be relatched and a new read cycle begun.
Table 10-21. GPMC Timing Parameters for Asynchronous Read Access
Parameter Name
Formula
Duration (ns)
Number of
GPMC Register
on GPMC side
Clock Cycles
Configurations
(F = 104 MHz)
ClkActivationTime
n/a (asynchronous mode)
AccessTime
round max (tCE)
80
9
ACCESSTIME = 0x09
PageBurstAccess
n/a (single access)
Time
RdCycleTime
Acce tOEZ
96, 615
11
RDCYCLETIME = 0x0B
CsOnTime
tCAS
0
0
CSONTIME = 0x0
CsReadOffTime
Acce 1 cycle
89, 615
10
CSRDOFFTIME = 0x0A
AdvOnTime
tAAVDS
3
1
ADVONTIME = 0X1
AdvRdOffTime
tAVDP
9
1
ADVRDOFFTIME =
0x01
OeOnTime
OeOnTime >= AdvRdOffTime
-
3 for instance
OEONTIME = 0x3
(multiplexed mode)
OeOffTime
Acce 1cycle
89, 615
10
OEOFFTIME = 0x0A
Figure 10-39. Asynchronous Single Read Access (Timing Parameters in Clock Cycles)
10.1.6.1.2.3 GPMC Configuration for Asynchronous Single Write Access
The clock runs at 104 MHz: (f = 104 MHz; T = 9, 615 ns).
shows how to calculate timings for the GPMC using the memory parameters.
shows the timing parameters (on the memory side) that determine the parameters on the
GPMC side.
shows the synchronous burst write access.
Table 10-22. AC Characteristics for Asynchronous Single Write ( Memory Side)
AC Characteristics on the Memory Side
Description
Duration (ns)
tWC
Write cycle time
60
tAVDP
nADV low time
6
tWP
Write pulse width
25
2190Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated