Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 2187 / 3738

GPMC module
Device
A [26:16]
CLK
RDY
nWP
nWE
nOE
nAVD
nCE
A/DQ [15:0]
A [27:17]
DEVICECLK
WP
WE
OE / RE
ADV /ALE
CS0
A [16:1] / D [15:0]
gpmc_a[11:1]
gpmc_clk
gpmc_wait0
gpmc_nwp
gpmc_nwe
gpmc_noe_nre
gpmc_nadv_ale
gpmc_ncs0
gpmc_d[15:0]
WAIT0
gpmc_037
NOR Flash
Public Version
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General-Purpose Memory Controller
Figure 10-37 shows the typical connection between the GPMC module and an attached NOR flash
memory.
Figure 10-37. GPMC Connection to an External NOR Flash Memory
The following sections demonstrate how to calculate GPMC parameters for three access types:
•
Synchronous burst read
• Asynchronous read
• Asynchronous single write
10.1.6.1.2.1 GPMC Configuration for Synchronous Burst Read Access
The clock runs at 104 MHz ( f = 104 MHz; T = 9, 615 ns).
Table 10-18 shows the timing parameters (on the memory side) that determine the parameters on the
GPMC side.
Table 10-19 shows how to calculate timings for the GPMC using the memory parameters.
Figure 10-38 shows the synchronous burst read access.
Table 10-18. Useful Timing Parameters on the Memory Side
AC Read Characteristics on the Description Duration (ns)
Memory Side
tCES nCS setup time to clock 0
tACS Address setup time to clock 3
tIACC Synchronous access time 80
2187 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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