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General-Purpose Memory Controller
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The message is mapped in the NAND starting with the highest-order parameters, that is, in the lowest
addresses of a NAND page.
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Byte endianness within the NANDs 16-bit words is big endian. This means that the same message
mapped in 8- and 16-bit memories has the same content at the same byte address.
NOTE:
The BCH module has no visibility over actual addresses. The most important point is the
sequence of data word the BCH sees. However, the NAND page is always scanned
incrementally in read and write accesses, which produces the mapping patterns described in
the following.
and
describe the mapping of the same 512-byte vector (typically a BCH message)
in the NAND memory space. The byte "address" is only an offset modulo 512 (0x200), because the same
page may contain several contiguous 512-byte sectors (BCH blocks). The LSB and MSB are respectively
the bits M0 and M(2
12
-1) of the codeword mapping given previously. In both cases the data vectors are
aligned; that is, their boundaries coincide with the RAMs data word boundaries.
Table 10-7. Aligned Message Byte Mapping in 8-bit NAND
Byte Offset
8-Bit Word
0x000
(msb) Byte 511 (0x1FF)
0x001
Byte 510 (0x1FE)
...
...
0x1FF
Byte 0 (0x0) (lsb)
Table 10-8. Aligned Message Byte Mapping in 16-bit NAND
Byte Offset
16-Bit Word MSB
16-Bit Word LSB
0x000
Byte 510 (0x1FE)
(msb) Byte 511 (0x1FF)
0x002
Byte 508 (0x1FC)
Byte 509 (0x1FD)
...
...
...
0x1FE
Byte 0 (0x0)
(lsb) Byte 1 (0x1)
through
show the mapping in memory of arbitrarily-sized messages, starting on
access (byte or 16-bit word) boundaries for more clarity. The message may actually start and stop on
arbitrary nibbles. A nibble is a 4-bit entity. The unused nibbles are not discarded; they can still be used by
the BCH module, but as part of the next message section (for example, on another sector ECC).
Table 10-9. Aligned Nibble Mapping of Message in 8-bit NAND
Byte Offset
8-Bit Word
4-Bit Most Significant Nibble
4-Bit Less Significant Nibble
1
(msb) Nibble S-1
Nibble S-2
2
Nibble S-3
Nibble S-4
...
...
...
S/2 - 2
Nibble 3
Nibble 2
S/2 - 1
Nibble 1
Nibble 0 (lsb)
2170Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
