MPU subsystem
DMA subsystem
Other
master
cores
On-chip
memory
(RAM/
ROM)
SDRAM Memory
Scheduler
SDRC
GPMC
L3 Interconnect
SDRAM
NOR, NAND
flash
Device
L3 interconnect
SDRAM controller subsystem
gpmc−001
Public Version
General-Purpose Memory Controller
www.ti.com
10.1 General-Purpose Memory Controller
10.1.1 General-Purpose Memory Controller Overview
The general-purpose memory controller (GPMC) is the device unified memory controller (UMC) dedicated
to interfacing external memory devices:
•
Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
•
Asynchronous, synchronous, and page mode burst NOR flash devices
•
NAND flash
•
Pseudo-SRAM devices
shows the environment of the GPMC.
Figure 10-1. GPMC Environment
10.1.1.1 GPMC Features
The GPMC is the device 16-bit external memory controller. The GPMC data access engine provides a
flexible programming model for communication with all standard memories. The GPMC supports various
accesses:
•
Asynchronous read/write access
•
Asynchronous read page access (4, 8, 16 Word16)
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Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
