Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 209 / 3738

Public Version
www.ti.com
L3 and L4 Memory Space Mapping
2.3 L3 and L4 Memory Space Mapping
The memory space system is hierarchical: L1, L2, L3, and L4.
L1 and L2 are memories in the MPU and IVA2.2 subsystems.
The chip-level interconnect, which consists of one L3 and four L4s, enables communication among all
modules and subsystems.
L3 handles many types of data transfers, including data exchange with system on-chip/external memories.
The four L4s handle transfers with peripherals, but are in four distinct power domains: the L4-Core,
L4-Wakeup, L4-Per, and L4-Emu interconnects, which are in the CORE, WKUP, PER, and EMU power
domains, respectively.
For more information about the interconnect, see Chapter 9 , Interconnect.
The following sections describe the register mapping of the L3 and L4 interconnects. Software configures
these registers.
2.3.1 L3 Memory Space Mapping
The L3 interconnect control registers are mapped in a 16-MB space and allow the configuration of the L3
interconnect parameters.
The L3 default settings are fully functional and enable all possible functional data paths. However, the
interconnect parameters can be changed to accommodate requirements.
Accesses to the L3 interconnect can be configured on a per-module basis using the internal L3 registers,
which are grouped into five register block types:
•
IA: Initiator agent configuration registers
• TA: Target agent configuration registers
• RT: Register target (global) configuration registers
• PM: Protection mechanism (firewalls) configuration registers
• SI: Global sideband signal configuration registers
For more information, see Chapter 9 , Interconnect.
This section describes all modules and features in the high-tier device. In unavailable modules and
features, the memory area is reserved, read is undefined, and write can lead to unpredictable behavior.
Table 2-2 describes the mapping of the L3 interconnect control registers.
Table 2-2. L3 Control Register Mapping
Device Name Start Address End Address Size (KB) Description
(Hex) (Hex)
L3 RT 0x6800 0000 0x6800 03FF 1 L3 configuration registers
L3 SI 0x6800 0400 0x6800 07FF 1 Sideband signal configuration
Reserved 0x6800 0800 0x6800 13FF 3 Reserved
MPU subsystem IA 0x6800 1400 0x6800 17FF 1 MPU subsystem instruction port agent
configuration
IVA2.2 subsystem IA 0x6800 1800 0x6800 1BFF 1 IVA2.2 subsystem initiator port agent
configuration
SGX subsystem IA 0x6800 1C00 0x6800 1FFF 1 SGX subsystem initiator port agent
configuration
SMS TA 0x6800 2000 0x6800 23FF 1 SMS target port agent configuration
GPMC TA 0x6800 2400 0x6800 27FF 1 GPMC target port agent configuration
OCM RAM TA 0x6800 2800 0x6800 2BFF 1 OCM RAM target port agent
configuration
OCM ROM TA 0x6800 2C00 0x6800 2FFF 1 OCM ROM target port agent
configuration
D2D IA 0x6800 3000 0x6800 33FF 1 Die-to-die (D2D) initiator port agent
configuration
209 SWPU177N – December 2009 – Revised November 2010 Memory Mapping
Copyright © 2009–2010, Texas Instruments Incorporated