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L4 Interconnects
9.3.1.1
L4-Core Interconnect
The L4-core interconnect handles only transfers to peripherals in the CORE power domain.
lists the TAs.
Table 9-104. L4-Core Target Agents
Module Name
Description
Display subsystem
Display subsystem configuration port
Camera subsystem
Camera subsystem port
USBHS OTG
Universal serial bus High-Speed port OTG
USBHS Host
Universal serial bus High-Speed port Host
USBTLL
USB Transceiver Less LInk
UART1
Universal asynchronous receiver transmitter port 1
UART2
Universal asynchronous receiver transmitter port 2
I2C1
Multimaster inter-integrated circuit 1
I2C2
Multimaster inter-integrated circuit 2
I2C3
Multimaster inter-integrated circuit 3
McBSP1
Multichannel buffered serial port 1
McBSP5
Multichannel buffered serial port 5
GPTIMER10
General-purpose timer 10
GPTIMER11
General-purpose timer 11
MMC1
Multimedia memory controller SDIO 1
MMC2
Multimedia memory controller SDIO 2
MMC3
Multimedia memory controller SDIO 3
HDQ/1-Wire
Single wire serial link low rate
MLB (mailbox)
Mailbox
MCSPI1
Serial peripheral interface 1
MCSPI2
Serial peripheral interface 2
MCSPI3
Serial peripheral interface 3
MCSPI4
Serial peripheral interface 4
SR1
SmartReflex1
SR2
SmartReflex2
sDMA
System DMA controller
L4-Wakeup
L4-Wakeup interconnect
CM
Clock manager
SCM
System control module
NOTE:
A unique port is used for communication between the L3 interconnect and the L4-Core
interconnect to allow the L3 initiators to access the L4-Core targets.
For the list of initiators authorized to access the L4-Core peripherals, see
. For
details on restricted access, see
, Protection Mechanism.
9.3.1.2
L4-Per Interconnect
The L4-Per interconnect handles only transfers to peripherals in the PER power domain.
lists
the TAs.
Table 9-105. L4-Per Target Agents
Module Name
Description
UARTIrDA
Universal asynchronous receiver/transmitter and infrared data
association port
2057
SWPU177N – December 2009 – Revised November 2010
Interconnect
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