Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1969 / 3738

Functional clock
Interface clock
Reset
Device
SGX
subsystem
MPU
subsystem
Interrupt
controller
SGX_IRQ
M_IRQ_21
SGX_FCLK
PRCM
L3
interconnect
SGX_ICLK SGX_L3_ICLK
SGX_RST SGX_RST
sgx-002
SGX_FCLK
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SGX Integration
8.2 SGX Integration
Figure 8-2 highlights the SGX subsystem integration in the device.
Figure 8-2. SGX Subsystem Integration
8.2.1 Clocking, Reset, and Power-Management Scheme
8.2.1.1 Clocks
The SGX subsystem operates from two clocks: an interface clock (SGX_ICLK) and a functional clock
(SGX_FCLK). The power, reset, and clock management (PRCM) module generates and distributes both
clocks inside the device. The SGX clock tree is depicted in the SGX Power Domain Clocking Scheme
figure in
Chapter 3 , Power, Reset, and Clock Management.
Table 8-1. Clock Descriptions
Signal Name I/O
(1)
Description
SGX_FCLK I Functional clock (two possible clock sources) → Functional clock domain
SGX_ICLK I Interface clock (L3 interconnect clock domain) → Interface clock domain
(1)
I =Input; O=Output
• The SGX_ICLK interface clock manages the data transfer on the L3 master and slave ports.
The source of SGX_ICLK is the PRCM clock (SGX_ICLK), which belongs to the SGX clock domain
and runs at the L3 interconnect clock speed. The SGX_ICLK frequency is selected based on the whole
device L3 interconnect clock frequency. For more information on the interface clock, see
Chapter 3 ,
Power, Reset, and Clock Management.
When no longer required by the SGX subsystem, SGX_ICLK can be disabled by software at the
PRCM level by setting the PRCM.CM_ICLKEN_SGX[0] EN_SGX bit to 0. For more information, see
the SGX Power Domain Clock Controls section in
Chapter 3 , Power, Reset, and Clock Management.
1969 SWPU177N – December 2009 – Revised November 2010 2D/3D Graphics Accelerator
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