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Display Subsystem Functional Description
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HS_INTER2 = BLANKING_PERIOD – (DDR_CL EXIT_CLK_H
DDR_ ENTER_HS_MODE_L 1)
HS_INTERLEAVING = min{ HS_INTER1, HS_INTER2}
•
Scenario 2: The gap for interleaving starts with a regular video stream HS packet and ends in LP state.
–
ddr_clk_always_on = 1
HS_INTERLEAVING = BLANKING_PERIOD – (EXIT_HS_MODE_L 3)
–
ddr_clk_always_on = 0
HS_INTER1 = BLANKING_PERIOD – (EXIT_HS_MODE_L 3)
HS_INTER1 = BLANKING_PERIOD – (DDR_CL EXIT_CLK_H 3)
HS_INTERLEAVING = min{ HS_INTER1, HS_INTER2}
•
Scenario 3: The gap for interleaving starts with the LP state and ends with a regular video stream HS
packet.
–
ddr_clk_always_on = 1
HS_INTERLEAVING = BLANKING_PERIOD – (ENTER_HS_MODE_L
EXIT_HS_MODE_L max{ ENTER_HS_MODE_LATENCY, 2} + 1)
–
ddr_clk_always_on = 0
HS_INTER1 = BLANKING_PERIOD – (DDR_C ENTER_HS_MODE_L
EXIT_HS_MODE_L max{ ENTER_HS_MODE_LATENCY, 2} + 1)
HS_INTER2 = BLANKING_PERIOD – (DDR_C ENTER_HS_MODE_L
DDR_CL EXIT_CLK_H DDR_ ENTER_HS_MODE_L
1)
HS_INTERLEAVING = min{ HS_INTER1, HS_INTER2})
•
Scenario 4: The gap for interleaving starts with the LP state and ends with a regular video stream HS
packet.
–
ddr_clk_always_on = 1
HS_INTERLEAVING = BLANKING_PERIOD – (ENTER_HS_MODE_L
EXIT_HS_MODE_L 3)
–
ddr_clk_always_on = 0
HS_INTER1 = BLANKING_PERIOD – (DDR_ ENTER_HS_MODE_L
EXIT_HS_MODE_L 3)
HS_INTER2 = BLANKING_PERIOD – (DDR_ ENTER_HS_MODE_L
DDR_CL EXIT_CLK_H 1)
HS_INTERLEAVING = min{ HS_INTER1, HS_INTER2}
7.4.3.3.5.2 LP Command Mode Interleaving Programming Model
shows the various LP mode scenarios in interleaving mode during a blanking gap. For each
type of blanking gap, a dedicated bit field determines the number of TxByteClkHS clock cycles used for
interleaving in LP command mode packets.
•
BL_LP_INTERLEAVING bit field
[15:0] defines the number of TxByteClkHS clock
cycles used to interleave the HS command mode packets during a BLLP gap.
•
HBP_LP_INTERLEAVING bit field
[7:0] defines the number of TxByteClkHS clock
cycles used to interleave the HS command mode packets during an HBP gap.
•
HFP_LP_INTERLEAVING bit field
[15:8] defines the number of TxByteClkHS clock
cycles used to interleave HS command mode packets during an HFP gap.
•
HSA_LP_INTERLEAVING bit field
[23:16] defines the number of TxByteClkHS clock
cycles used to interleave HS command mode packets during an HSA gap.
These programmable values must be programmed to satisfy the timings for clock and data lane enter and
exit LP mode latency. Clock lane timings do not affect LP command mode interleaving, because the clock
lane can be controlled separately, compared with the data lane high-speed and low-power mutually
exclusive control. Clock lanes can be in high-speed mode while the data lanes are in high-speed data
transfer mode, low-power data transfer mode, or in low-power state.
According to this scenario, different equations must be considered for calculating register values.
1668
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
