Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
Table 6-691. CSIPHY_REG1
Address Offset 0x0000 0004
Physical Address Instance See Table 6-80
See Table 6-688
Description Second Register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCLK_TERM DPHY_HS_SYNC_PATTERN TCLK_SETTLE
RESERVED RESERVED TCLK_MISS
RESETDONERXBYTECLK
RESETDONECSI2_96M_FCLK
CLOCK_MISS_DETECTOR_STATUS
Bits Field Name Description Type Reset
31:30 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
29 RESETDONECSI2_96M_FCLK Reset Done flag for the CSI2_96M_FCLK domain R 0x-
Read 0x0: Reset in progress
Read 0x1: Reset completed
28 RESETDONERXBYTECLK Reset Done flag for the RxByteClkHS clock domain R 0x-
Read 0x0: Reset in progress
Read 0x1: Reset completed
27:26 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0
25 CLOCK_MISS_DETECTOR_ST 1:Error in clock missing detector. 0:Clock missing R 0
ATUS detector successful
24:18 TCLK_TERM Tclk-term timing parameter in multiples of RW 0x00
CSI2_96M_FCLK period.
Requirement from DSI_PHY spec = (Dn Voltage < 450
mV) –55 ns.
Effective time for enabling termination = synchonizer
delay + timer delay + LPRx delay + combinatorial routing
delay
~ (1–2)*CSI2_96 Tclk-term + ~ (1–15) ns.
Programmed value = ceil(9.5 ns/CSI2_96M_FCLK
period)–1).
Default value: 0 for 96 MHz.
Note: 5 percent clock frequency tolerance.
17:10 DPHY_HS_SYNC_PATTERN DPHY mode HS sync pattern in byte order(reverse of RW 0xB8
received order)
9:8 TCLK_MISS Tclk-miss timing parameter in multiples of RW 0x1
CSI2_96M_FCLK period
Programmed value = ceil(15 ns/CSI2_96M_FCLK
period)–1
Default value: 1 for 96 MHz
1555 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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