Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
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Table 6-689. CSIPHY_REG0
Address Offset 0x0000 0000
Physical Address Instance See Table 6-80
See Table 6-688
Description First Register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED THS_TERM THS_SETTLE
HSCLOCKCONFIG
Bits Field Name Description Type Reset
31:25 RESERVED Write 0s for future compatibility. Read returns 0. NA 0x00
24 HSCLOCKCONFIG Disable clock missing detector RW 0
23:16 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00
15:8 THS_TERM Ths-term timing parameter in multiples of RW 0x04
CSI2_96M_FCLK period.
Requirement from DSI_PHY spec = (Dn Voltage < 450
mV) –35 ns + 4 UI.
Effective time for enabling termination = synchonizer
delay + timer delay + LPRx delay + combinatorial routing
delay ~ (1–2)* Ths-term + ~ (1–15) ns.
Programmed value = ceil(12.5 ns/DDRClk period)–1.
Default value: 4 for 400 MHz.
Note: 20 percent clock frequency tolerance.
7:0 THS_SETTLE Ths-settle timing parameter in multiples of DDR clock RW 0x27
period.
Derived requirement from DSI_PHY spec = (90 ns + 6
UI) – (145 ns + 10 UI).
Effective Ths-settle seen on the line (starting to look for
sync pattern) = synchonizer delay + timer delay + LPRx
delay + combinatorial routing delay – pipeline delay in HS
data path.
~ (1–2)* Ths- ~ (1–15) ns – 1*DDRClk
Programmed value = ceil(90 ns/DDR clock 3.
Default value: 39 for 400 MHz.
Note:
1. Minimum supported Ths-settle preprogrammed value
= 3.
2. One clock delay in datapath from HSRx must be
compensated. Hence + 3.
Table 6-690. Register Call Summary for Register CSIPHY_REG0
Camera ISP Basic Programming Model
• Camera ISP CSIPHY Initialization for Work With CSI2 Receiver : [0]
Camera ISP Register Manual
• Camera ISP CSIPHY Register Summary : [1]
1554 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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