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Camera ISP Basic Programming Model
Table 6-74. Camera ISP H3A AEW Engine Required Configuration Parameters (continued)
Function
Configuration Required
Window start and size information
Memory address
6.5.9.2
Camera ISP H3A Enable/Disable Hardware
Setting the
[0] AF_EN bit enables the AF engine, and the
[16] AEW_EN bit enables
the AEW engine. This should be done after all required registers are programmed.
The H3A always operates in continuous mode. Because the input to the H3A module is the video-port
interface of the CCDC, processing of the frame depends on the timing signals from the CCDC. To ensure
that data from the CCDC is not missed, the H3A should be enabled before the CCDC so that it waits for
CCDC data.
The AF engine or the AEW engine can be disabled by clearing the
[0] AF_EN or
[16]
AEW_EN bit, respectively, during the processing of the last frame. The disable is latched in at the end of
the frame in which it is written.
6.5.9.3
Camera ISP H3A Event and Status Checking
Both the AF engine and the AEW engine generate an interrupt at the end of processing each frame.
These interrupt events can be sent to CAM_IRQ0 or CAM_IRQ1 by setting the H3A_AWB_DONE_IRQ or
H3A_AF_DONE_IRQ bits in the
enable register (or
The status of these interrupts can be checked by reading the
register (or
). When the read of the register
occurs (or
), the
register is not automatically reset. To reset the interrupt, a 1 must be written to the corresponding bit.
Each event that generates an interrupt can be individually mapped to ARM or DSP using the
register (or
). When a particular event is not enabled (for example
[x] = 0), the correspondent status (
[x] = 1) bit is flagged if the
correspondent event occurs. This has no effect on the interrupt line, but can be used by software to poll
the status.
6.5.9.4
Camera ISP H3A Register Accessibility During Frame Processing
There are two types of register access in the H3A module:
•
Shadow registers: These registers/fields can be read and written (if the field is writable) at any time.
However, the written values take effect only at the start of a frame. Reads return the most recent write,
even though the settings are not used until the next start of frame.
The shadowed registers are:
–
–
–
•
Busy-lock registers:
–
All registers EXCEPT the shadowed registers belong to this category.
–
Busy-lock registers cannot be written when the module is busy. Writes are allowed, but no change
occurs in the registers (blocked writes from hardware perspective, but allowed writes from software
perspective).
–
After the busy bit in the PCR register is reset to 0, the busy-lock registers can be written (
[15] BUSYAF for AF registers and
[18] BUSYAEAWB for AE/AWB registers).
The ideal procedure for changing the H3A registers is:
1291
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated
