1
2
3
4
5
6
7
8
3
1
C
C
P2
_
L
C
M_
VSIZ
E
[27
:16
]C
O
U
N
T
CCP2_LCM_CTRL[7:5] BURST_SIZE
CCP2_LCM_PREFETCH[13:3] HWORDS
CCP2_LCM_SRC_OFST[31:5] OFST
camisp-207
Max allowed burst size used
Smaller burst used
Read data
Unused data
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Camera ISP Functional Description
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Table 6-26. Camera ISP CSI1/CCP2B Data Packing Benefit and Constraints
Bits Per Pixel
Storage Reduction
Width Multiple
(1)
Packed
Unpacked
RAW6
6
8
25%
16
RAW7
7
8
13%
32
RAW8
8
8
0%
4
RAW10
10
16
38%
16
RAW12
12
16
25%
8
(1)
In continuous mode, lines must be multiples of 128 bits. In 2D mode, lines must start on 128-bit boundaries.
6.4.2.2.5.2 Camera ISP CSI1/CCP2B Memory Read Port Burst Generation
The hardware always uses the largest possible burst size according to the setup. The amount of data read
from memory can be higher than what is actually used by the CCP2B receiver. Only full 64-bit words are
read.
shows the data organization in memory.
Figure 6-65. Camera ISP CSI1/CCP2B Data Organization in Memory 3
NOTE:
•
A minimum burst size of 2 must be selected for correct operation.
•
HWORDS must be paired for correct operation.
shows the relationship between the different parameters controlling the burst generation. The
1172
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated