Receive Buffer
UCxRXBUF
Receive Shift Register
Transmit Buffer
UCxTXBUF
Transmit Shift Register
SPI Receive Buffer
Data Shift Register (DSR)
UCx
SOMI
SOMI
UCxSIMO
SIMO
MASTER
SLAVE
Px.x
STE
UCxSTE
SS
Port.x
UCxCLK
SCLK
MSP430 USCI
COMMON SPI
USCI Operation – SPI Mode
972
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Universal Serial Communication Interface – SPI Mode
NOTE:
Default character format
The default SPI character transmission is LSB first. For communication with other SPI
interfaces, MSB-first mode may be required.
NOTE:
Character format for Figures
Figures throughout this chapter use MSB-first format.
37.3.3 Master Mode
Figure 37-2. USCI Master and External Slave
shows the USCI as a master in both 3-pin and 4-pin configurations. The USCI initiates data
transfer when data is moved to the transmit data buffer UCxTXBUF. The UCxTXBUF data is moved to the
transmit (TX) shift register when the TX shift register is empty, initiating data transfer on UCxSIMO starting
with either the MSB or LSB, depending on the UCMSB setting. Data on UCxSOMI is shifted into the
receive shift register on the opposite clock edge. When the character is received, the receive data is
moved from the receive (RX) shift register to the received data buffer UCxRXBUF and the receive
interrupt flag UCRXIFG is set, indicating the RX/TX operation is complete.
A set transmit interrupt flag, UCTXIFG, indicates that data has moved from UCxTXBUF to the TX shift
register and UCxTXBUF is ready for new data. It does not indicate RX/TX completion.
To receive data into the USCI in master mode, data must be written to UCxTXBUF, because receive and
transmit operations operate concurrently.
37.3.3.1 4-Pin SPI Master Mode
In 4-pin master mode, UCxSTE is used to prevent conflicts with another master and controls the master
as described in
. When UCxSTE is in the master-inactive state:
•
UCxSIMO and UCxCLK are set to inputs and no longer drive the bus.
•
The error bit UCFE is set, indicating a communication integrity violation to be handled by the user.
•
The internal state machines are reset and the shift operation is aborted.
If data is written into UCxTXBUF while the master is held inactive by UCxSTE, it is transmit as soon as
UCxSTE transitions to the master-active state. If an active transfer is aborted by UCxSTE transitioning to
the master-inactive state, the data must be rewritten into UCxTXBUF to be transferred when UCxSTE
transitions back to the master-active state. The UCxSTE input signal is not used in 3-pin master mode.