USCI_A UART Mode Registers
962
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Universal Serial Communication Interface – UART Mode
36.4.7 UCAxRXBUF Register
USCI_Ax Receive Buffer Register
Figure 36-18. UCAxRXBUF Register
7
6
5
4
3
2
1
0
UCRXBUFx
r
r
r
r
r
r
r
r
Table 36-13. UCAxRXBUF Register Description
Bit
Field
Type
Reset
Description
7-0
UCRXBUFx
R
undefined
The receive-data buffer is user accessible and contains the last received
character from the receive shift register. Reading UCAxRXBUF resets the
receive-error bits, the UCADDR or UCIDLE bit, and UCRXIFG. In 7-bit data
mode, UCAxRXBUF is LSB justified and the MSB is always reset.
36.4.8 UCAxTXBUF Register
USCI_Ax Transmit Buffer Register
Figure 36-19. UCAxTXBUF Register
7
6
5
4
3
2
1
0
UCTXBUFx
rw
rw
rw
rw
rw
rw
rw
rw
Table 36-14. UCAxTXBUF Register Description
Bit
Field
Type
Reset
Description
7-0
UCTXBUFx
RW
undefined
The transmit data buffer is user accessible and holds the data waiting to be
moved into the transmit shift register and transmitted on UCAxTXD. Writing to
the transmit data buffer clears UCTXIFG. The MSB of UCAxTXBUF is not used
for 7-bit data and is reset.