USCI_A UART Mode Registers
959
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Universal Serial Communication Interface – UART Mode
36.4.2 UCAxCTL1 Register
USCI_Ax Control Register 1
Figure 36-13. UCAxCTL1 Register
7
6
5
4
3
2
1
0
UCSSELx
UCRXEIE
UCBRKIE
UCDORM
UCTXADDR
UCTXBRK
UCSWRST
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-1
Can be modified only when UCSWRST = 1.
Table 36-8. UCAxCTL1 Register Description
Bit
Field
Type
Reset
Description
7-6
UCSSELx
RW
0h
USCI clock source select. These bits select the BRCLK source clock.
00b = UCAxCLK (external USCI clock)
01b = ACLK
10b = SMCLK
11b = SMCLK
5
UCRXEIE
RW
0h
Receive erroneous-character interrupt enable
0b = Erroneous characters rejected and UCRXIFG is not set.
1b = Erroneous characters received set UCRXIFG.
4
UCBRKIE
RW
0h
Receive break character interrupt enable
0b = Received break characters do not set UCRXIFG.
1b = Received break characters set UCRXIFG.
3
UCDORM
RW
0h
Dormant. Puts USCI into sleep mode.
0b = Not dormant. All received characters set UCRXIFG.
1b = Dormant. Only characters that are preceded by an idle-line or with address
bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the
combination of a break and synch field sets UCRXIFG.
2
UCTXADDR
RW
0h
Transmit address. Next frame to be transmitted is marked as address, depending
on the selected multiprocessor mode.
0b = Next frame transmitted is data.
1b = Next frame transmitted is an address.
1
UCTXBRK
RW
0h
Transmit break. Transmits a break with the next write to the transmit buffer. In
UART mode with automatic baud-rate detection, 055h must be written into
UCAxTXBUF to generate the required break/synch fields. Otherwise, 0h must be
written into the transmit buffer.
0b = Next frame transmitted is not a break.
1b = Next frame transmitted is a break or a break/synch.
0
UCSWRST
RW
1h
Software reset enable
0b = Disabled. USCI reset released for operation.
1b = Enabled. USCI logic held in reset state.