Texas Instruments MSP430x4xx Family, User Manual

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USCI Registers: SPI Mode
20-14 Universal Serial Communication Interface, SPI Mode
20.4 USCI Registers: SPI Mode
The USCI registers applicable in SPI mode for USCI_A0 and USCI_B0 are
listed in Table 20−2. Registers applicable in SPI mode for USCI_A1 and
USCI_B1 are listed in Table 20−3.
Table 20−2.USCI_A0 and USCI_B0 Control and Status Registers
Register Short Form Register Type Address Initial State
USCI_A0 control register 0 UCA0CTL0 Read/write 060h Reset with PUC
USCI_A0 control register 1 UCA0CTL1 Read/write 061h 001h with PUC
USCI_A0 Baud rate control register 0 UCA0BR0 Read/write 062h Reset with PUC
USCI_A0 Baud rate control register 1 UCA0BR1 Read/write 063h Reset with PUC
USCI_A0 modulation control register UCA0MCTL Read/write 064h Reset with PUC
USCI_A0 status register UCA0STAT Read/write 065h Reset with PUC
USCI_A0 Receive buffer register UCA0RXBUF Read 066h Reset with PUC
USCI_A0 Transmit buffer register UCA0TXBUF Read/write 067h Reset with PUC
USCI_B0 control register 0 UCB0CTL0 Read/write 068h 001h with PUC
USCI_B0 control register 1 UCB0CTL1 Read/write 069h 001h with PUC
USCI_B0 Bit rate control register 0 UCB0BR0 Read/write 06Ah Reset with PUC
USCI_B0 Bit rate control register 1 UCB0BR1 Read/write 06Bh Reset with PUC
USCI_B0 status register UCB0STAT Read/write 06Dh Reset with PUC
USCI_B0 Receive buffer register UCB0RXBUF Read 06Eh Reset with PUC
USCI_B0 Transmit buffer register UCB0TXBUF Read/write 06Fh Reset with PUC
SFR interrupt enable register 2 IE2 Read/write 001h Reset with PUC
SFR interrupt flag register 2 IFG2 Read/write 003h 00Ah with PUC
Note: Modifying SFR bits
To avoid modifying control bits of other modules, it is recommended to set
or clear the IEx and IFGx bits using
BIS.B
or
BIC.B
instructions, rather than
MOV.B
or
CLR.B
instructions.