Texas Instruments MSP430x4xx Family, User Manual

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USCI Operation: SPI Mode
20-11 Universal Serial Communication Interface, SPI Mode
20.3.6 Serial Clock Control
UCxCLK is provided by the master on the SPI bus. When UCMST = 1, the bit
clock is provided by the USCI bit clock generator on the UCxCLK pin. The clock
used to generate the bit clock is selected with the UCSSELx bits. When
UCMST = 0, the USCI clock is provided on the UCxCLK pin by the master, the
bit clock generator is not used, and the UCSSELx bits are don’t care. The SPI
receiver and transmitter operate in parallel and use the same clock source for
data transfer.
The 16-bit value of UCBRx in the bit rate control registers UCxxBR1 and
UCxxBR0 is the division factor of the USCI clock source, BRCLK. The
maximum bit clock that can be generated in master mode is BRCLK.
Modulation is not used in SPI mode and UCAxMCTL should be cleared when
using SPI mode for USCI_A. The UCAxCLK/UCBxCLK frequency is given by:
f
BitClock
+
f
BRCLK
UCBRx
Serial Clock Polarity and Phase
The polarity and phase of UCxCLK are independently configured via the
UCCKPL and UCCKPH control bits of the USCI. Timing for each case is shown
in Figure 20−4.
Figure 20−4. USCI SPI Timing with UCMSB = 1
CKPH CKPL
Cycle#
UCxCLK
UCxCLK
UCxCLK
UCxCLK
UCxSIMO/
UCxSOMI
UCxSIMO
UCxSOMI
Move to UCxTXBUF
RX Sample Points
0
1
0
0
0 1
1 1
0 X
1 X
MSB
MSB
1 2 3 4 5 6 7 8
LSB
LSB
TX Data Shifted Out
UCxSTE
UC UC