Timer_B Operation
16-6
Timer_B
Up Mode
The up mode is used if the timer period must be different from TBR
(max)
counts.
The timer repeatedly counts up to the value of compare latch TBCL0, which
defines the period, as shown in Figure 16−2. The number of timer counts in
the period is TBCL0+1. When the timer value equals TBCL0 the timer restarts
counting from zero. If up mode is selected when the timer value is greater than
TBCL0, the timer immediately restarts counting from zero.
Figure 16−2. Up Mode
0h
TBR(max)
TBCL0
The TBCCR0 CCIFG interrupt flag is set when the timer counts to the TBCL0
value. The TBIFG interrupt flag is set when the timer counts from TBCL0 to
zero. Figure 15−3 shows the flag set cycle.
Figure 16−3. Up Mode Flag Setting
TBCL0−1
TBCL0
0h
Timer Clock
Timer
Set TBIFG
Set TBCCR0 CCIFG
1h
TBCL0−1
TBCL0
0h
Changing the Period Register TBCL0
When changing TBCL0 while the timer is running and when the TBCL0 load
event is immediate, CLLD0 = 00, if the new period is greater than or equal to
the old period, or greater than the current count value, the timer counts up to
the new period. If the new period is less than the current count value, the timer
rolls to zero. However, one additional count may occur before the counter rolls
to zero.
Summary of Contents for MSP430x4xx Family
Page 1: ...MSP430x4xx Family 2007 Mixed Signal Products User s Guide SLAU056G ...
Page 2: ......
Page 6: ...vi ...
Page 114: ...3 76 RISC 16 Bit CPU ...
Page 304: ...5 20 FLL Clock Module ...
Page 340: ...7 8 Supply Voltage Supervisor ...
Page 348: ...8 8 16 Bit Hardware Multiplier ...
Page 372: ...9 24 32 Bit Hardware Multiplier ...
Page 400: ...10 28 DMA Controller ...
Page 428: ...13 10 Basic Timer1 ...
Page 466: ...15 24 Timer_A ...
Page 522: ...17 30 USART Peripheral Interface UART Mode ...
Page 544: ...18 22 USART Peripheral Interface SPI Mode ...
Page 672: ...23 12 Comparator_A ...
Page 692: ...24 20 LCD Controller ...
Page 746: ...26 28 ADC12 ...