Texas Instruments MSP430x4xx Family, User Manual

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Flash Memory Operation
6-7 Flash Memory Controller
6.3.2 Erasing Flash Memory
The erased level of a flash memory bit is 1. Each bit can be programmed from
1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The
smallest amount of flash that can be erased is a segment. Erase modes are
selected with the GMERAS (MSP430FG461x devices), MERAS and ERASE
bits listed in Table 6−1, Table 6−2 and Table 6−3.
Table 6−1. MSP430FG461x Erase Modes
GMERAS MERAS ERASE Erase Mode
X 0 1 Segment erase
0 1 0 Mass erase (all main memory segments
of selected memory array)
0 1 1 Erase all flash memory (main and infor-
mation segments of selected memory
array)
1 1 0 Global mass erase (all main memory seg-
ments of both memory arrays)
1 1 1 Erase main memory and information seg-
ments of both memory arrays
Table 6−2. MSP430F47x Erase Modes
MERAS ERASE Erase Mode
0 1 Segment erase
1 0 Mass erase (all main memory segments)
1 1 LOCKA = 0: Erase main and information flash memory.
LOCKA = 1: Erase only main flash memory.
Table 6−3. Erase Modes
MERAS ERASE Erase Mode
0 1 Segment erase
1 0 Mass erase (all main memory segments)
1 1 Erase all flash memory (main and information segments)
Any erase is initiated by a dummy write into the address range to be erased.
The dummy write starts the flash timing generator and the erase operation.
Figure 6−4 shows the erase cycle timing. The BUSY bit is set immediately after
the dummy write and remains set throughout the erase cycle. BUSY, GMERAS
(when present), MERAS, and ERASE are automatically cleared when the
cycle completes. The erase cycle timing is not dependent on the amount of
flash memory present on a device. Erase cycle times are device-specific; see
the device data sheet.