Texas Instruments MSP430x11x1 Specification Sheet Download Page 41

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

Port P2, P2.5, input/output with Schmitt-trigger and R

OSC

function for the Basic Clock module

See Note 27

See Note 28

See Note 27

GND

VCC

P2.5

Interrupt

Edge

Select

Set

P2IE.5

P2IFG.5

P2IRQ.5

Interrupt
Flag

P2IES.5

P2SEL.5

Module X IN

P2IN.5

P2OUT.5

Module X OUT

Direction Control

From Module

P2DIR.5

P2SEL.5

Pad Logic

NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad

Bus Keeper

VCC

Internal to
Basic Clock
Module

DCOR

DC
Generator

0: Input

1: Output

CAPD.5

PnSel.x

PnDIR.x

Direction

control from

module

PnOUT.x

Module X OUT

PnIN.x

Module X IN

PnIE.x

PnIFG.x

PnIES.x

P2Sel.5

P2DIR.5

P2OUT.5

VSS

P2IN.5

unused

P2IE.5

P2IFG.5

P2IES.5

NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.

28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

Summary of Contents for MSP430x11x1

Page 1: ... code efficiency The digitally controlled oscillator provides fast wake up from all low power modes to active mode in less than 6 ms Typical applications include sensor systems that capture analog signals convert them to digital values and then process the data and display them or transmit them to a host system Stand alone RF sensor front end is another area of application The I O port inputs prov...

Page 2: ...set I O Port P1 8 I O s All With Interrupt CPU Incl 16 Reg Test JTAG Bus Conv MAB 16 Bit MDB 16 Bit MAB 4 Bit MDB 8 Bit MCB XIN XOUT VCC VSS RST NMI P1 0 7 DCOR ACLK P2 0 ACLK Rosc TEST F Flash Outx Timer_A 3 CC CCR0 1 2 Watchdog Timer 15 16 Bit MCLK x 0 1 2 ACLK SMCLK Outx CCIx CCIx TACLK or INCLK INCLK Out0 CCI0 JTAG CCIxA TACLK SMCLK I O Port P2 6 I O s All With 8 Capabililty Interrupt Capabili...

Page 3: ...se digital I O pin ACLK output P2 1 INCLK 9 I O General purpose digital I O pin Timer_A clock signal at INCLK P2 2 CAOUT TA0 10 I O General purpose digital I O pin Timer_A capture CCI0B input comparator_A output P2 3 CA0 TA1 11 I O General purpose digital I O pin Timer_A compare Out1 output comparator_A input P2 4 CA1 TA2 12 I O General purpose digital I O pin Timer_A compare Out2 output comparato...

Page 4: ...addressing modes are listed in Table 2 Table 1 Instruction Word Formats Dual operands source destination e g ADD R4 R5 R4 R5 R5 Single operands destination only e g CALL R8 PC TOS R8 PC Relative jump un conditional e g JNE Jump on equal bit 0 Most instructions can operate on both word and byte data Byte operations are identified by the suffix B Examples Instructions for word operation Instructions...

Page 5: ...on to the mode that was selected before the interrupt event The different requirements of the CPU and modules which are driven by system cost and current consumption objectives necessitate the use of different clock signals D Auxiliary clock ACLK from LFXT1CLK crystal s frequency used by the peripheral modules D Main system clock MCLK used by the CPU and system D Subsystem clock SMCLK used by the ...

Page 6: ...when SCG0 is reset The dc generator can be deactivated only if the SCG0 bit is set and the DCOCLK signal is not used for MCLK or SMCLK The current consumed by the dc generator defines the basic frequency of the DCOCLK It is a dc current The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCG0 bit is set There are two situations when the SCG0 bit cannot switch off t...

Page 7: ...ble non maskable 0FFFCh 14 0FFFAh 13 0FFF8h 12 Comparator_A CAIFG maskable 0FFF6h 11 Watchdog timer WDTIFG maskable 0FFF4h 10 Timer_A CCIFG0 Note 2 maskable 0FFF2h 9 Timer_A CCIFG1 CCIFG2 TAIFG Notes 1 and 2 maskable 0FFF0h 8 0FFEEh 7 0FFECh 6 0FFEAh 5 0FFE8h 4 I O Port P2 eight flags see Note 3 P2IFG 0 to P2IFG 7 Notes 1 and 2 maskable 0FFE6h 3 I O Port P1 eight flags P1IFG 0 to P1IFG 7 Notes 1 a...

Page 8: ... WDTIE 3 2 1 rw 0 rw 0 rw 0 Address 0h NMIIE ACCVIE rw 0 WDTIE Watchdog timer enable signal OFIE Oscillator fault enable signal NMIIE Nonmaskable interrupt enable signal ACCVIE Access violation at flash memory 7 6 5 4 0 3 2 1 Address 01h interrupt flag register 1 and 2 7 6 5 4 0 OFIFG WDTIFG 3 2 1 rw 0 rw 1 rw 0 Address 02h NMIIFG WDTIFG Set on overflow or security key violation or Reset on VCC po...

Page 9: ...per download environment The bootstrap loader is only available on F devices functions of the bootstrap loader Definition of read apply and transmit data of peripheral registers or memory to pin P1 1 BSLTX write read data from pin P2 2 BSLRX and write them into flash memory unprotected functions Mass erase erase of the main memory Segment0 to Segment7 Access to the MSP430 via the bootstrap loader ...

Page 10: ...tor D Basic clock module Rsel 5 DCO 4 MOD 0 DCOCLK for MCLK and SMCLK clock divider for MCLK and SMCLK at default dividing by 1 D Timer_A Timer_A operates in continuous mode with MCLK source selected input divider set to 1 using CCR0 and polling of CCIFG0 D WDT Watchdog timer is halted D Interrupt GIE 0 NMIIE 0 OFIFG 0 ACCVIFG 0 D Memory allocation and stack pointer If the stack pointer points to ...

Page 11: ...the internal TEST signal is held low and the pins remain in the application mode RST NMI PIN TEST Internal TEST PIN Bootstrap loader Starts VCC Test mode can be entered again after TEST is taken low and then back high The bootstrap loader will not be started via the vector in address 0C00h if D There were less than two positive edges at TEST while RST NMI is low D TEST is low if RST NMI goes from ...

Page 12: ... completed During program or erase no code can be executed from flash memory and all interrupts must be disabled by setting the GIE NMIE ACCVIE and OFIE bits to zero If a user program requires execution concurrent with a flash program or erase operation the program must be executed from memory other than the flash memory e g boot ROM RAM In the event a flash program or erase operation is initiated...

Page 13: ... and ACVIFG is set SEGWRT 0128h bit7 Bit SEGWRT may be used to reduce total programming time Refer to MSP430x1xx User s Guide literature number SLAU049 for details 0 1 No segment write acceleration is selected Segment write is used This bit needs to be reset and set between segment borders Table 3 Allowed Combinations of Control Bits Allowed for Flash Memory Access FUNCTION PERFORMED SEGWRT WRT ME...

Page 14: ...X BUSY WAIT Write 1 to Figure 1 Flash Memory Timing Generator Diagram FCTL2 012Ah FN2 FN1 FN0 0 rw 0 rw 1 rw 0 7 rw 0 SSEL0 rw 1 FN5 FN4 FN3 15 FCTL2 read 096h FCTL2 write 0A5h rw 0 rw 0 rw 0 8 SSEL1 The control bits are FN0 FN5 012Ah bit0 5 These six bits define the division rate of the clock signal The division rate is 1 to 64 according to the digital value of FN5 to FN0 plus one SSEL0 SSEL1 012...

Page 15: ...violated 1 Key 0A5h high byte was violated Violation occurs when a write access to registers FCTL1 FCTL2 or FCTL3 is executed and the high byte is not equal to 0A5h If the security key is violated bit KEYV is set and a PUC is performed ACCVIFG 012Ch bit2 Access violation interrupt flag The access violation flag is set when any combination of control bits other than those shown in Table 3 is attemp...

Page 16: ...h memory module while the lock bit is set EMEX 012Ch bit5 Emergency exit The emergency exit should only be used if the flash memory write or erase operation is out of control 0 No function 1 Stops the active operation immediately and shuts down all internal parts in the flash memory controller Current consumption immediately drops back to the active mode All bits in control register FCTL1 are rese...

Page 17: ...r VCC POR PUC WDTQn EQU PUC POR PUC POR NMIRS Clear S WDTIFG IRQ WDTIE Clear IE1 0 PUC POR IRQA TIMSEL Counter IFG1 0 NMI TMSEL NMIES Watchdog Timer Module Clear S IFG1 4 PUC Clear IE1 4 PUC NMIFG NMIIE S IFG1 1 Clear IE1 1 PUC OFIFG OFIF OSCFault NMI_IRQA IRQA Interrupt Request Accepted RST NMI S FCTL1 1 Clear IE1 5 ACCVIFG ACCVIE PUC ACCV WDT Figure 2 Block Diagram of NMI Interrupt Sources ...

Page 18: ...eration SMCLK can be generated from LFXT1CLK or DCOCLK ACLK is always generated from LFXT1CLK The crystal oscillator can be defined to operate with watch crystals 32768 Hz or with higher frequency ceramic resonators or crystals The crystal or ceramic resonator is connected across two terminals No external components are required for watch crystal operation If the high frequency XT1 mode is selecte...

Page 19: ...e nominal DCO frequency is defined by the dc generator and can be set by one external resistor or can be set to one of eight values with integrated resistors Additional adjustments and modulations of DCOCLK are possible by software manipulation of registers in the DCO module DCOCLK is stopped automatically when it is not used by the CPU or peripheral modules The dc generator can be shut down with ...

Page 20: ...password in the high byte The low byte stores data written to the WDTCTL The high byte must be the password 05Ah If any value other than 05Ah is written to the high byte of the WDTCTL a system reset PUC is generated When the password is read its value is 069h This minimizes accidental write operations to the WDTCTL register In addition to the watchdog timer control bits there are two bits included...

Page 21: ... P2 2 P1 2 CAOUT P1 3 ACLK Out 0 Out 1 Out 2 Capture Compare Register CCR2 Figure 4 Timer_A MSP430x11x1 Configuration Two interrupt vectors are used by the Timer_A module One individual vector is assigned to capture compare block CCR0 and one common interrupt vector is implemented for the timer and the other two capture compare blocks The three interrupt events using the same vector are identified...

Page 22: ...d observation of external analog signals The comparator is connected to port pins P2 3 CA0 and to P2 4 CA1 It is controlled via twelve control bits in registers CACTL1 and CACTL2 P2 3 CA0 TA1 P2CA0 P2 4 CA1 TA2 0 1 0 1 P2CA1 0 1 0 1 _ CAON 0 1 CAEX 0 1 CAF Low Pass Filter τ 2 0 µs CCI1B Set CAIFG Flag CAOUT 0 CARSEL 1 0 2 1 3 VCAREF 0 1 2 3 CAREF 0 5 x VCC 0 25 x VCC CA1 CA0 P2 2 CAOUT TA0 0 V 0 V...

Page 23: ...G 1 The falling edge set the Comparator_A interrupt flag CAIFG CAON 059h bit3 The comparator is switched on CAREF 059h bit4 5 Comparator_A reference 0 Internal reference is switched off an external reference can be applied 1 0 25 VCC reference selected 2 0 50 VCC reference selected 3 A diode reference selected CARSEL 059h bit6 An internal reference VCAREF selected by CAREF bits can be applied to s...

Page 24: ... CAPD5 CAPD6 CAPD7 NOTE Ensure that the comparator input terminals are connected to signal power or ground level Otherwise floating levels may cause unexpected interrupts and current consumption may be increased slope a d conversion The Comparator_A is well suited for use in single or multiple slope conversions The internal reference levels may be used to set a reference during timing measurement ...

Page 25: ...8h Watchdog Watchdog timer control WDTCTL 0120h PERIPHERALS WITH BYTE ACCESS Comparator_A Comparator_A port disable Comparator_A control2 Comparator_A control1 CAPD CACTL2 CACTL1 05Bh 05Ah 059h System Clock Basic clock sys control2 Basic clock sys control1 DCO clock freq control BCSCTL2 BCSCTL1 DCOCTL 058h 057h 056h Port P2 Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select P...

Page 26: ...SS 0 V Operating free air temperature range TA MSP430x11x1 40 85 C LFXT1 t l f LF mode selected XTS 0 Watch crystal 32768 Hz LFXT1 crystal frequency f LFXT1 see Note 6 XT1 mode selected XTS 1 Ceramic resonator 450 8000 kHz f LFXT1 see Note 6 XT1 mode selected XTS 1 Crystal 1000 8000 kHz VCC 1 8 V MSP430x11x1 dc 2 Processor frequency f system MCLK signal VCC 2 2 V MSP430x11x1 dc 5 MHz VCC 3 6 V MSP...

Page 27: ...ating conditions continued 5 MHz at 2 2 V MSP430x11x1 Devices NOTE Minimum processor frequency is defined by system clock Flash program or erase operations require a minimum VCC of 2 7 V 9 3 2 1 0 0 1 2 3 4 4 VCC Supply Voltage V 8 MHz at 3 6 V 5 6 7 8 2 MHz at 1 8 V Maximum Processor Frequency MHz f system Figure 6 Frequency vs Supply Voltage ...

Page 28: ...1x1 f MCLK 0 f SMCLK 1 MHz f ACLK 32 768 Hz VCC 3 V 55 70 I LPM2 Low power mode LPM2 TA 40 C 85 C f MCLK f SMCLK 0 MHz VCC 2 2 V 11 14 µA I LPM2 Low power mode LPM2 f MCLK f SMCLK 0 MHz f ACLK 32 768 Hz SCG0 0 VCC 3 V 17 22 µA I LPM3 Low power mode LPM3 TA 40 C 85 C f MCLK f SMCLK 0 MHz VCC 2 2 V 1 2 1 7 µA I LPM3 C11x1 f MCLK f SMCLK 0 MHz f ACLK 32 768 Hz SCG0 1 VCC 3 V 2 2 7 µA TA 40 C 0 8 1 2 ...

Page 29: ...2 V See Note 10 VCC 0 25 VCC VOH High level output voltage I OHmax 3 4 mA VCC 2 2 V See Note 10 VCC 0 6 VCC V VOH g g Port 2 F11x1 I OHmax 1 mA VCC 3 V See Note 10 VCC 0 25 VCC V I OHmax 3 4 mA VCC 3 V See Note 10 VCC 0 6 VCC I OLmax 1 5 mA VCC 2 2 V See Note 8 VSS VSS 0 25 VOL Low level output voltage Port 1 and Port 2 C11x1 I OLmax 6 mA VCC 2 2 V See Note 9 VSS VSS 0 6 V VOL Port 1 and Port 2 C1...

Page 30: ...V 3 V 1 5 cycle t int External interrupt timing Port P1 P2 P1 x to P2 x External trigger signal for the interrupt flag 2 2 V 62 ns see Note 14 3 V 50 ns 2 2 V 3 V 1 5 cycle t cap Timer_A capture timing TA0 TA1 TA2 see Note 15 2 2 V 62 ns 3 V 50 ns NOTES 14 The external signal sets the interrupt flag every time the minimum tint cycle and time parameters are met It may be set even with triggersignal...

Page 31: ...REF 1 2 3 No load at P2 3 CA0 TA1 and P2 4 CA1 TA2 VCC 3 V 45 71 µA V IC Common mode input voltage CAON 1 VCC 2 2 V 3 V 0 VCC 1 V V Ref025 See Figure 5 Voltage 0 25 V CC node V CC PCA0 1 CARSEL 1 CAREF 1 No load at P2 3 CA0 TA1 and P2 4 CA1 TA2 See Figure 5 VCC 2 2 V 3 V 0 23 0 24 0 25 V Ref050 See Figure 5 Voltage 0 5 V CC node V CC PCA0 1 CARSEL 1 CAREF 2 No load at P2 3 CA0 TA1 and P2 4 CA1 TA2...

Page 32: ...rating free air temperature unless otherwise noted continued 450 500 550 600 650 700 45 25 5 15 35 55 75 Temperature C V RefVT 95 Mean 6 Sigma Mean 4 Sigma Mean 4 Sigma Mean 6 Sigma Mean Figure 7 V RefVT vs Temperature VCC 3 V C1121 450 500 550 600 650 700 45 25 5 15 35 55 75 Temperature C V RefVT 95 Mean 6 Sigma Mean 4 Sigma Mean 4 Sigma Mean 6 Sigma Mean Figure 8 V RefVT vs Temperature VCC 2 2 V...

Page 33: ...continued _ CAON 0 1 V 0 1 CAF Low Pass Filter τ 2 0 µs To Internal Modules Set CAIFG Flag CAOUT V VCC 1 0 V 0 Figure 9 Block Diagram of Comparator_A Module Overdrive VCAOUT t response V V 400 mV Figure 10 Overdrive Definition PUC POR PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t POR_delay 150 250 µs TA 40 C 1 4 1 8 V V POR POR TA 25 C VCC 2 2 V 3 V 1 1 1 5 V TA 85 C VCC 2 2 V 3 V 0 8 1 2 V V min 0...

Page 34: ... oscillator LFXT1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT C XIN Input capacitance XTS 0 LF mode selected VCC 2 2 V 3 V 12 pF C XIN Input capacitance XTS 1 XT1 mode selected VCC 2 2 V 3 V Note 19 2 pF C XOUT Output capacitance XTS 0 LF mode selected VCC 2 2 V 3 V 12 pF C XOUT Out ut ca acitance XTS 1 XT1 mode selected VCC 2 2 V 3 V Note 19 2 F NOTE 19 Requires external capacitors at both termina...

Page 35: ...CO53 R l 5 DCO 3 MOD 0 DCOR 0 TA 25 C VCC 2 2 V 1 1 2 1 5 MHz f DCO53 Rsel 5 DCO 3 MOD 0 DCOR 0 TA 25 C VCC 3 V 1 1 3 1 5 MHz f DCO63 R l 6 DCO 3 MOD 0 DCOR 0 TA 25 C VCC 2 2 V 1 6 1 9 2 2 MHz f DCO63 Rsel 6 DCO 3 MOD 0 DCOR 0 TA 25 C VCC 3 V 1 69 2 2 29 MHz f DCO73 R l 7 DCO 3 MOD 0 DCOR 0 TA 25 C VCC 2 2 V 2 4 2 9 3 4 MHz f DCO73 Rsel 7 DCO 3 MOD 0 DCOR 0 TA 25 C VCC 3 V 2 7 3 2 3 65 MHz f DCO77...

Page 36: ...CC 2 2 V 3 V 6 µs f MCLK 3 MHz VCC 2 2 V 3 V 6 NOTE 22 Parameter applicable only if DCOCLK is used for MCLK JTAG programming PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f TCK TCK frequency JTAG test see Note 25 VCC 2 2 V dc 5 MHz f TCK TCK frequency JTAG test see Note 25 VCC 3 V dc 10 MHz V FB Fuse blow voltage C versions see Notes 23 and 24 VCC 2 2 V 3 V 3 5 3 9 V I FB Supply current on TDI during...

Page 37: ...Logic NOTE x Bit identifier 0 to 3 for port P1 PnSel x PnDIR x Direction control from module PnOUT x Module X OUT PnIN x Module X IN PnIE x PnIFG x PnIES x P1Sel 0 P1DIR 0 P1DIR 0 P1OUT 0 VSS P1IN 0 TACLK P1IE 0 P1IFG 0 P1IES 0 P1Sel 1 P1DIR 1 P1DIR 1 P1OUT 1 Out0 signal P1IN 1 CCI0A P1IE 1 P1IFG 1 P1IES 1 P1Sel 2 P1DIR 2 P1DIR 2 P1OUT 2 Out1 signal P1IN 2 CCI1A P1IE 2 P1IFG 2 P1IES 2 P1Sel 3 P1DI...

Page 38: ...a smaller external pulldown resistor in some applications x Bit identifier 4 to 7 for port P1 During programming activity and during blowing the fuse the pin TDO TDI is used to apply the test input for JTAG circuitry P1 7 TDI TDO P1 6 TDI P1 5 TMS P1 4 TCK Typical TEST GND NOTE Fuse not implemented in F11x1 PnSel x PnDIR x Direction control from module PnOUT x Module X OUT PnIN x Module X IN PnIE ...

Page 39: ...IR x P2SEL x Pad Logic NOTE x Bit Identifier 0 to 2 for port P2 0 Input 1 Output Bus Keeper CAPD X PnSel x PnDIR x Direction control from module PnOUT x Module X OUT PnIN x Module X IN PnIE x PnIFG x PnIES x P2Sel 0 P2DIR 0 P2DIR 0 P2OUT 0 ACLK P2IN 0 unused P2IE 0 P2IFG 0 P1IES 0 P2Sel 1 P2DIR 1 P2DIR 1 P2OUT 1 VSS P2IN 1 INCLK P2IE 1 P2IFG 1 P1IES 1 P2Sel 2 P2DIR 2 P2DIR 2 P2OUT 2 CAOUT P2IN 2 C...

Page 40: ...lect EN Set Q P2IE 4 P2IFG 4 P2IRQ 4 Interrupt Flag P2IES 4 P2SEL 4 Module X IN P2IN 4 P2OUT 4 Module X OUT Direction Control From Module P2DIR 4 P2SEL 4 Pad Logic 0 Input 1 Output Bus Keeper CAPD 4 _ Comparator_A Reference Block CAREF CAREF CAEX P2CA CAF CCI1B 0 V VCC GND APPLICATION INFORMATION PnSel x PnDIR x Direction control from module PnOUT x Module X OUT PnIN x Module X IN PnIE x PnIFG x P...

Page 41: ...Direction Control From Module P2DIR 5 P2SEL 5 Pad Logic NOTE DCOR Control bit from Basic Clock Module if it is set P2 5 Is disconnected from P2 5 pad Bus Keeper 0 1 0 1 VCC Internal to Basic Clock Module DCOR DC Generator 0 Input 1 Output CAPD 5 PnSel x PnDIR x Direction control from module PnOUT x Module X OUT PnIN x Module X IN PnIE x PnIFG x PnIES x P2Sel 5 P2DIR 5 P2DIR 5 P2OUT 5 VSS P2IN 5 un...

Page 42: ...ed P2IE 6 P2IFG 6 P2IES 6 P2Sel 7 P2DIR 7 P2DIR 7 P2OUT 7 VSS P2IN 7 unused P2IE 7 P2IFG 7 P2IES 7 NOTE A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags The interrupt flags can not be influenced from any signal other than from software They work then as a soft interrupt JTAG fuse check mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mod...

Page 43: ... 0 004 0 10 A 8 16 0 020 0 51 0 014 0 35 0 293 7 45 0 299 7 59 9 0 010 0 25 0 050 1 27 0 016 0 40 15 24 15 49 PINS 0 010 0 25 NOM A MAX DIM A MIN Gage Plane 20 0 500 12 70 12 95 0 510 10 16 10 41 0 400 0 410 16 0 600 24 0 610 0 004 0 10 M 0 010 0 25 0 050 1 27 0 8 NOTES A All linear dimensions are in inches millimeters B This drawing is subject to change without notice C Body dimensions do not inc...

Page 44: ... 50 0 75 0 15 NOM Gage Plane 28 9 80 9 60 24 7 90 7 70 20 16 6 60 6 40 4040064 F 01 97 0 30 6 60 6 20 8 0 19 4 30 4 50 7 0 15 14 A 1 1 20 MAX 14 5 10 4 90 8 3 10 2 90 A MAX A MIN DIM PINS 0 05 4 90 5 10 Seating Plane 0 8 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion not to exceed 0 15 D ...

Page 45: ... this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards ...

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